Refactor the FSP-M early Sign-of-Life (eSOL) implementation to utilize
the UX APIs defined in `ux.c`.
This eliminates redundant code and ensures consistent messaging during
critical boot phases, such as memory training.
BUG=b:339673254
TEST=Verified eSOL message over eDP while booting google/fatcat.
Change-Id: Icf22c39c21e2357b2a548398700a1488f4ef463a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch refactors the eSOL implementation for Panther Lake and
introduces two new APIs, mirroring those in Alder Lake, to manage:
- Low battery shutdown notifications
- Firmware update memory training
BUG=b:397302064
TEST=Built and booted google/fatcat successfully.
Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86509
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the SoC-specific implementation of the early
low-battery shutdown notification. The generic implementation now
resides within the FSP driver layer, requiring only platform-specific
customization.
Platforms can now implement platform_display_early_shutdown_notification()
when CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) is enabled. This
function utilizes ux_inform_user_of_poweroff_operation() to display a
"low-battery shutdown" message using libgfxinit.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: If9f68b2b5cc710e00584b451f904e60d724d1e32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86453
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an early low-battery shutdown mechanism during
FSP memory initialization. This is particularly important during
firmware updates, where memory training can consume significant power
and lead to abrupt shutdowns, potentially corrupting the firmware.
The changes include:
- Adding platform_display_early_shutdown_notification() to notify the
user of the impending shutdown.
- Checking platform_is_low_battery_shutdown_needed() to determine if a
shutdown is necessary.
- Implementing a shutdown sequence if low battery is detected during
memory init, especially when no MRC cache is found (i.e. firmware
update).
- Deferring shutdown on systems without MAINBOARD_HAS_EARLY_LIBGFXINIT
so that FSP-M (uGOP) can display a message.
This prevents firmware update corruption due to low battery.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86452
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit activates the Firmware Support Package (FSP) Memory
Sign-of-Life feature (FSP_UGOP_EARLY_SIGN_OF_LIFE), which allows for the
display of a user-configurable text message on-screen during memory
initialization. This feature enhances the user experience by providing
reassurance that the memory training process is underway and may take
some time.
The following FSP-M UPDs (Updateable Product Data) are utilized:
- VgaInitControl (boolean): Initializes graphics, establishes VGA text
mode, and centers the VgaMessage text on the screen. It clears the
screen, disables VGA text mode, and deactivates graphics upon exiting
the FSP-M (Firmware Support Package - Memory Initialization).
- VbtPtr (address): This is a pointer to the VBT (Video BIOS Table)
binary.
- VbtSize (unsigned integer): Indicates the size of the VBT binary.
- LidStatus (boolean): Given the limited resources available at early
boot stages, the text message is shown on a single monitor. The lid
status determines the most appropriate display to use:
- 0: If the lid is closed, display the text message on an external
display if one is available; otherwise, display nothing.
- 1: If the lid is open, display the message on the internal display;
if unavailable, default to an external display.
- VgaMessage (string): Specifies the text message to be displayed.
When the FSP_UGOP_EARLY_SIGN_OF_LIFE flag is set, coreboot is configured
to use the UPDs mentioned above to show a text message during the memory
training phase. This text message can be customized through the locale
text mechanism using the identifier memory_training_desc.
In addition, the newly introduced code records an extra event to
indicate when early Sign-Of-Life has been requested, to cover the Memory
Reference Code (MRC) training scenario. This event logging is crucial
for debugging and analyzing the boot process, especially in production
environments where it helps in pinpointing the exact stage where a boot
issue might occur.
TEST="Enabling FSP-M Sign-of-Life" message is present in the log upon
the first boot, and a message is displayed on the screen while the
FSP performs MRC training.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85454
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In the low battery poweroff scenario, the platform should halt after
issuing the poweroff command. This ensures that no further code
execution occurs, preventing potential issues.
Additionally, the do_low_battery_poweroff() function is marked with
__noreturn to indicate that it does not return. This is appropriate
because the platform will either power off or halt.
TEST=Able to compile google/fatcat.
Change-Id: Ieb77645283360b5731ca48b94551712b99109a1c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86578
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry.
It is annoying when searching for the wrong abbreviation in the spec so
fix it everywhere it occurs.
source: Intel 64 spec April 2022 and AMD64 spec April 2024.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I730235beea69b3720f080bbade083c2eeed26587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
HWRot (Hardware Root of trust) is not used, so we disable its clocks to
save power. This patch is a subitem of Vcore power consumption
improvement. The whole work improves SoC power consumption from 120mW to
90mW in suspend.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK & Suspend/Resume passed
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86553
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit `fb2c09d516` stopped the SSDT
containing TPM tables if PTT was not active, as at the time, the
table unconditionally reported the device present in the _STA
method.
Commit `d503ce1277` made the _STA to
return an accurate state, so now, the tables can always be
generated and Linux will report the presence correctly.
Change-Id: I594bf25a207b809c1ae2632eb1aea0d0fb6df35e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If CONFIG(CRB_TPM) is enabled but the TPM is inactive, and no other TPM
interface (SPI, I2C, Memory-Mapped) is configured, the function would
incorrectly fallback to generate a TPM2 table for FIFO mode.
This commit adds a check to ensure crb_tpm_is_active() is only
called if CONFIG(CRB_TPM) is enabled and no other TPM interface
is present. If the CRB TPM is inactive and no other TPMs are
available, the function now exits early to prevent generating
an invalid TPM2 table.
Test=boot `starlabs/starlite_adl` and check Linux doesn't probe for a
TPM when PTT is not active.
Change-Id: I153779aa1f3d84ffeb694543f9da1d09b120f98f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
List of changes -
1. Make GPP_B3 IRQ only pin.
2. Remove redundant GPE option from touchpad device.
BUG=b:397905085
TEST=Verified wake from S0ix using touchpad.
Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Manually confgiure the vGPIO's related to CNVi for USB Bluetooth
instead of UART.
Change-Id: I7d6007e40b2edbadeb5611f6cd67df0c1e6ee8a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86565
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO is not connected, so configure it accordingly.
Change-Id: I4b3421f1ab676599ffec6b2f46429ce937704e40
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86564
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace all occurrences of u8, u16, u32 and u64 with their respective
alternatives of uint8_t. There is no need to unnecessarily compress code
by using standard types aliases.
BUG=b:391874512
TEST=Compile cbmem
Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
It seems FSP will only automatically configure the vGPIO's for
CNVi Bluetooth if USB 2 Port 7 is used. On this board, USB 2
Port 9 is used, so manually confgiure the vGPIO's related to
CNVi for USB Bluetooth instead of UART.
Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard is marked IQ1X0MS, though it is also known as the MS-7988.
The Small Form Factor version was used for this port, though the Mini
Tower seems to use the exact same board. Other systems such as the
ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre
700-25ISH appear to use the same PCB with different configurations of
components.
All the code in this port was originally copied from the Asrock H110M
and then modified to match the actual configuration of the M900. The VBT
was extracted using `intelvbttool -l -v data.vbt` while running version
FWKTBFA of the vendor firmware.
Working:
- Boots to Linux with SeaBIOS 1.16.3
- Boots to Linux with EDK2 (MrChromebox uefipayload_202408)
- Display Ports
- VGA port
- PCIe slots
- Console over serial port
- Front and rear USB 3.0 ports and internal USB2.0 headers
- Front and rear audio jacks
- Internal speaker
- SATA ports 1-4 (5 and 6 are not populated on the M900)
- Hardware monitoring via nct6683 kernel module
- Gigabit Ethernet
- S3 suspend/resume
Unknown/untested:
- M.2 E-key slot
- Parallel port header
- PS/2 Mouse/Keyboard via KB_MS1 header
- TPM
Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB.
BUG=b:379008996
BRANCH=none
TEST=booted successfully
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86538
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move gpio_get_eint_reg() and gpio_calc_eint_pos_bit() to common code
to avoid redundant definitions for other platforms such as MT8189.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id21f627a49f730f3a0db786a148f81806aeba287
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the HAVE_ACPI_RESUME config option from the Google
Brya mainboard configuration. The Intel Alder Lake SoC does not support
S3 (ACPI sleep state) entry/exit, and attempting S3 validation could
lead to abnormal platform behavior. This change ensures that `_S3` is
not listed as a valid wake source in the DSDT (Differentiated System
Description Table) after booting to the OS.
BUG=b:337274309
TEST=Boot verfied google/trulo.
TEST=Veified that the _S3 name variable is not present in the DSDT ASL.
Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86422
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the vendorcode openSIL memory map code and move all common
calls that do not require any openSIL headers to the driver. Improve
the legibility of the logic to return memory hole type string.
Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need to know how many combo entries have been processed.
It will be checked in functions in later change.
Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85590
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up the code to make it more logical.
This is for later changes to reorder the PSP Level 1, Level 2, ISH and
BIOS tables.
TEST=Identical test on all AMD platform
Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84531
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For A/B recovery, it is better, even though it is not mandatory, to
put BIOS level 2 table next to its PSP level2. So the relative
addresses of BIOS table are the same. So all the data in B could be a
copy of A.
Identical binary test on all non A/B recovery platform.
Booting test on Majolica with A/B recovery enabled.
Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The current SMBIOS for fatcat is missing processor upgrade information.
This patch adds the missing value by enabling kconfig flag
CPU_INTEL_SOCKET_OTHER.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
Output of dmidecode:
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPU0
Type: Central Processor
Family: Pentium Pro
Manufacturer: GenuineIntel
ID: C0 06 0C 00 FF FB EB BF
Signature: Type 0, Family 6, Model 204, Stepping 0
Flags: ...
Version: Genuine Intel(R) 0000
Voltage: Unknown
External Clock: 100 MHz
Max Speed: 3200 MHz
Current Speed: 3000 MHz
Status: Populated, Enabled
- Upgrade: Unknown
+ Upgrade: Other
BUG=NONE
TEST=Boot and verified that SMBIOS processor upgrade value is correct.
Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Fix USB port assignments/descriptions to match actual topology.
TEST=build/boot Win11 on starlabs/starbook_adl_n. Verify ports
match assignmented in devicetree using USBTreeview.
Change-Id: If0b341f1c5f99b53df8fff69f8a58fa732adbbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Unselect LIBGFXINIT to bring these two variants inline with the
others.
Change-Id: If0fdc9ffd391f2710f252be7358d87644a77b36a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
According to the design, the SPI ROM will be replaced
with a 16MB size, so the Kconfig is modified to 16MB.
BUG=b:397372760
TEST=emerge-nissa coreboot and check rom size is 16MB
Change-Id: I3ef1aa2401d44259e4301f65e2ba0ac7b9418bbd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86501
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the meliks variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:394359785
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MELIKS
Change-Id: Iff5e27ef06a44976c2724751de0f9c6d5cf6eaaf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86373
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Uldrenite will support internal fivr in next phase and using fw_config
to decide the board with internal or external fivr.
BUG=b:394752422
BRANCH=firmware-trulo-15217.771.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally
Change-Id: I14233090f2445461cf422c1257f21556fd745b43
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86303
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Improve SSD reset time by enabling earlier sequencing, save 230ms
BUG=b:397098950
TEST=build and boot normal using NVMe
Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This GPIO should be NF2, not NF1.
Change-Id: I012acfa43ada5641b37f38892a1e3bfbc6e74843
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Frostflow is a 2-in-1 device, this sets the SMBIOS enclosure type
properly.
Change-Id: I6c3306270cbc80bb55fb536a1fc51a5546287649
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Cave is a 2-in-1 device, this sets the SMBIOS enclosure type properly.
Change-Id: I8f2ec82c97676aa315c18286b5e2eb94d46004ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Set these to minipc and all-in-one respectively now that these
system types exist, so that the SMBIOS enclosure type is correctly
set vs defaulting to desktop.
Change-Id: I661401dcd7fe348a07e34ace309c0a8b7e0f00eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Puff variants will now correctly show their SMBIOS type as an
all-in-one (dooly, scout) or a mini-pc (all other variants) rather than
the default desktop type.
Change-Id: Id24ff40f0aacade359f281def8be2a41c752d0d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Jecht variants will now correctly show their SMBIOS type as mini-pc
rather than the default desktop type.
Change-Id: I4f1be147bcfdad6247101db5b5943301466e60ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Fizz variants will now correctly show their SMBIOS type as an
all-in-one (karma) or a mini-pc (all other variants) rather than the
default desktop type.
Change-Id: Ida61c68d3664115ca29cb11e6820edb1496e4709
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86458
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cyan and Kefka are convertible devices, so set them as such so their
SMBIOS type is set correctly, necessary for some Linux tablet drivers.
Change-Id: Ief81c7ba83eb5326dd6199508a3194008dee243b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86457
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Beltino variants will now correctly show their SMBIOS type as an
all-in-one (monroe) or a mini-pc (all other variants) rather than the
default desktop type.
Change-Id: Ia9f17236c415b626fd5d553a453cf43d4145ef41
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86456
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the newly-added SYSTEM_TYPE_ALL_IN_ONE for Buddy variant, and
use that as a discriminator to de-duplicate selections for system
type and HAVE_SPD_IN_CBFS.
Change-Id: I0d28bc496ff6bcfa9947a4d15ed2d8f75cf74ac3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
1. K3KL9L90CM-MGCT (SAMSUNG)
2. H58G66BK8BX067 (HYNIX)
BUG=b:388117663
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I1ca97e28852660cae0352d771e30c9348a5939a0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86477
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
