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treewide: Rename PM4LE -> PML4E

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The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry.
It is annoying when searching for the wrong abbreviation in the spec so
fix it everywhere it occurs.

source: Intel 64 spec April 2022 and AMD64 spec April 2024.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I730235beea69b3720f080bbade083c2eeed26587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
This commit is contained in:
Maximilian Brune 2025-02-24 17:21:35 +01:00 • committed by Jérémy Compostella
commit a8139c0b87
12 changed files with 22 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

4
payloads/libpayload/arch/x86/head_64.S
View file

@ -70,7 +70,7 @@ _entry:
movl %eax, cb_header_ptr
call init_page_table
movl $pm4le, %eax
movl $pml4e, %eax
/* load identity mapped page tables */
movl %eax, %cr3
@ -107,7 +107,7 @@ _init64:
movq %rdi, cb_header_ptr
call init_page_table
movq $pm4le, %rax
movq $pml4e, %rax
/* load identity mapped page tables */
movq %rax, %cr3

8
payloads/libpayload/arch/x86/pt.S
View file

@ -41,10 +41,10 @@
#define _D (1ULL << 6)
#define _PS (1ULL << 7)
.section .bss.pm4le
.global pm4le
.section .bss.pml4e
.global pml4e
.align 4096
pm4le:
pml4e:
.skip 8
.section .bss.main_page_table
@ -144,6 +144,6 @@ no_overflow_1gb:
leave:
or $(_PRES + _RW + _US + _A), %eax
mov %eax, pm4le
mov %eax, pml4e
ret

2
src/cpu/intel/car/core2/cache_as_ram.S
View file

@ -163,7 +163,7 @@ addrsize_set_high:
subl $4, %esp
#if ENV_X86_64
setup_longmode $PM4LE
setup_longmode $PML4E
movd %mm2, %rdi
shlq $32, %rdi

2
src/cpu/intel/car/non-evict/cache_as_ram.S
View file

@ -214,7 +214,7 @@ end_microcode_update:
andl $0xfffffff0, %esp
#if ENV_X86_64
setup_longmode $PM4LE
setup_longmode $PML4E
movd %mm2, %rdi
shlq $32, %rdi

2
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View file

@ -363,7 +363,7 @@ fill_cache:
subl $4, %esp
#if ENV_X86_64
setup_longmode $PM4LE
setup_longmode $PML4E
movd %mm2, %rdi
shlq $32, %rdi /* BIST */

2
src/cpu/x86/64bit/mode_switch2.S
View file

@ -21,7 +21,7 @@ long_mode_call_3arg:
mov %esp, %ebp
/* Enter long mode, preserves ebx */
setup_longmode $PM4LE
setup_longmode $PML4E
/* Align stack */
movabs $0xfffffffffffffff0, %rax

4
src/cpu/x86/64bit/pt.S
View file

@ -17,9 +17,9 @@
#define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a))
#define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
.global PM4LE
.global PML4E
.align 4096
PM4LE:
PML4E:
.quad _GEN_DIR(PDPT)
.align 4096

4
src/cpu/x86/64bit/pt1G.S
View file

@ -17,9 +17,9 @@
#define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a))
#define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
.global PM4LE
.global PML4E
.align 4096
PM4LE:
PML4E:
.quad _GEN_DIR(PDPT)
.align 4096

10
src/cpu/x86/smm/smm_module_loader.c
View file

@ -420,27 +420,27 @@ static int append_and_check_region(const struct region smram,
#define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
#define PAGE_SIZE 8
/* Return the PM4LE */
/* Return the PML4E */
static uintptr_t install_page_table(const uintptr_t handler_base)
{
const bool one_g_pages = !!(cpuid_edx(0x80000001) & (1 << 26));
/* 4 1G pages or 4 PDPE entries with 512 * 2M pages */
const size_t pages_needed = one_g_pages ? 4 : 2048 + 4;
const uintptr_t pages_base = ALIGN_DOWN(handler_base - pages_needed * PAGE_SIZE, 4096);
const uintptr_t pm4le = ALIGN_DOWN(pages_base - 8, 4096);
const uintptr_t pml4e = ALIGN_DOWN(pages_base - 8, 4096);
if (one_g_pages) {
for (size_t i = 0; i < 4; i++)
write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(1ull * GiB * i));
write64p(pm4le, _GEN_DIR(pages_base));
write64p(pml4e, _GEN_DIR(pages_base));
} else {
for (size_t i = 0; i < 2048; i++)
write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(2ull * MiB * i));
write64p(pm4le, _GEN_DIR(pages_base + 2048 * PAGE_SIZE));
write64p(pml4e, _GEN_DIR(pages_base + 2048 * PAGE_SIZE));
for (size_t i = 0; i < 4; i++)
write64p(pages_base + (2048 + i) * PAGE_SIZE, _GEN_DIR(pages_base + 4096 * i));
}
return pm4le;
return pml4e;
}
/*

2
src/soc/amd/common/block/cpu/noncar/pre_c.S
View file

@ -28,7 +28,7 @@ bootblock_pre_c_entry:
post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64
setup_longmode $PM4LE
setup_longmode $PML4E
#endif
/* Clear .bss section */

2
src/soc/intel/common/block/cpu/car/cache_as_ram.S
View file

@ -280,7 +280,7 @@ car_init_done:
andl $0xfffffff0, %esp
#if ENV_X86_64
setup_longmode $PM4LE
setup_longmode $PML4E
movd %mm2, %rdi
shlq $32, %rdi

2
src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
View file

@ -83,7 +83,7 @@ CAR_init_done:
movl %ecx, temp_memory_start
#if ENV_X86_64
setup_longmode $PM4LE
setup_longmode $PML4E
movl %ebp, %edi
shlq $32, %rdi
movd %mm1, %rsi