To allow doing DRAM initialization in ROM stage instead of BootROM, we need to
move bootblock and ROM stage base address into iRAM, also the stack and CBFS
cache area just like TTB.
BUG=none
TEST=Boots on Nyan without problem.
Change-Id: I459faef5eb0f75561089dafbb111ae83729c3a29
Reviewed-on: https://chromium-review.googlesource.com/179822
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Add iRAM layout in Kconfig comments so we can know how and where to utilize iRAM
in future.
BUG=none
TEST=none # simply adding comments.
Change-Id: I77ec661e6980ad7d77a9c26840bd911a555cc37c
Reviewed-on: https://chromium-review.googlesource.com/179814
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Make sure reg_script is executed before the device is put into
ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi from eMMC in ACPI mode
Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pull the ACPI GNVS pointer from CBMEM and expose it in
the sysinfo structure for use by payloads.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode
Change-Id: I47c358f33c464a4a01080268fb553705218c940c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This will make it possible for payloads to find the ACPI
NVS region which is needed to get base addresses for devices
that are in ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode
Change-Id: Ia67b66ee8bd45ab8270444bbb2802080d31d14eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since this file will get added to payloads it is useful if it
exports what offset in NVS it lives.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode
Change-Id: I52860980c91dfe2525628e142b34ca192e69b258
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Correct norrin display specific settings. Drop venice2 supporting
functions.
norrin display code needs to be clean up.
BUG=None
TEST=built, flash and boot, graphic shown up
BRANCH=None
Change-Id: If62028b6f5cb101c4898f7198c3e057f2bac61f3
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/179745
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
In order to use the same reference code on S3 resume
that was booted the program needs to be cached. Piggy
back on the ramstage cache to save the loaded reference
code program.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed. Noted locations of reference
code caching and load addresses in console.
Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179777
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
To prepare for caching reference code for S3 resume the
ramstage cache needs to be accesible in ramstage as well.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Allow ramstage cache to be used from ramstage proper. Also
add a helper function for checking validity of ramstage
cache structure.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179775
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Certain code paths want to know if S3 resume is
happening. However, the current baytrail code doesn't
note S3 resume early enough. Therefore, mark S3
resume just after pattr setup.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179774
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The inclusion of reg_script_run_on_dev() allows
for removing some of the chained reg_scripts just
to set up the device context. Use the new reg_script
function in those cases.
BUG=None
BRANCH=None
TEST=Built and booted. Didn't see any bizarre dmesg or coreboot
console output.
Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438
Signed-off-by: Aaron Durbin <adurbin@chromium.og>
Reviewed-on: https://chromium-review.googlesource.com/179541
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
According to the reference code all these registers
need to be set to their best known values.
BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted. Suspend and wake. No idea about
observable impact yet.
Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179749
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There's a slew of ports required to initialize baytrail's
perf and power values. Therefore, add the necessary
functionality in the iosf module as well as the reg_script
library.
BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted.
Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179748
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The iosf access functions already use some common code,
however there is a duplication for setting up the proper
control register for port and opcode. Introduce macros
to remove this verbosity.
BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted. Suspend and wake.
Change-Id: I5bad7e2a11fa8e8bd4a3d7fa53d917b2565644f8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179747
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This additional CFLAGS makes it build without have to wrap the make in magic.
BUG=None
TEST=libpayload builds for ARM
BRANCH=None
Change-Id: Ie9a6239e2864734788c5b72f65a7523635ccf75c
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178757
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This patch adds a new static assertion macro that can be used to check
the offsets in structures that overlay register sets at compile time. It
uses the _Static_assert() declaration from the new ISO C11 standard,
which is supported (even without -std=c11) by GCC after version 4.6.
(There is supposedly also support in clang, although I haven't tried
it... let's deal with compiler issues when/if they turn up.)
I've added it to all structures for our current ARM SoCs for now, and I
think every new register overlay we add going forward should use them
(at least for the last member, but feel free to add more if you think
it's useful).
BUG=None
TEST=Compiled for Snow, Pit and Nyan.
Change-Id: If32510e7049739ad05618d363a854dc372d64386
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179412
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The reg_script library has proven to be useful. It's
also shown that many scripts operate on devices. However,
certain code paths run the same script on multiple,
but different, devices. In order to make that easier
introduce reg_script_run_on_dev() which takes a device
as a parameter. That way, chained reg_scripts are not
scrictly needed to run the same script on multiple devices.
BUG=None
BRANCH=None
TEST=Built.
Change-Id: I273499af4d303ebd7dc19e9b635ca23cf9bb2225
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179540
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This adds the option to put LPSS and SCC devices into ACPI mode
by saving their BAR0 and BAR1 base addresses in a new device
NVS structure that is placed at offset 0x1000 within the global
NVS table.
The Chrome NVS strcture is padded out to 0xf00 bytes so there
is a clean offset to work with as it will need to be used by
depthcharge to know what addresses devices live at.
A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and
the EMMC 4.5 IRQ is changed to 44.
New ACPI code is provided to instantiate the LPSS and SCC devices
with the magic HID values from Intel so the kernel drivers can
locate and use them.
The default is still for devices to be in PCI mode so this does
not have any real effect without it being enabled in the mainboard
devicetree.
Note: this needs the updated IASL compiler which is in the CQ now
because it uses the FixedDMA() ACPI operator.
BUG=chrome-os-partner:23505,chrome-os-partner:24380
CQ-DEPEND=CL:179459,CL:179364
BRANCH=none
TEST=manual tests on rambi device:
1) build and boot with devices still in PCI mode and ensure that
nothing is changed
2) enable lpss_acpi_mode and see I2C devices detected by the kernel
in ACPI mode. Note that by itself this breaks trackpad probing so
that will need to be implemented before it is enabled.
3) enable scc_acpi_mode and see EMMC and SDCard devices detected by
the kernel in ACPI mode. Note that this breaks depthcharge use of
the EMMC because it is not longer discoverable as a PCI device.
Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179481
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This enables the DPTF framework, but it doesn't do much
without some sort of kernel+user components to drive it.
BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF
Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179480
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is not complete yet but it compiles and doesn't cause
any issues by itself. It is tied into the EC pretty closely
so that is part of the same commit.
Once we have more of the EC support done it will need some
more work to make use of those new interfaces properly.
BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF
Change-Id: I4b27e38baae18627a275488d77944208950b98bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179459
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are the values that are seen with VBIOS and
may need tweaked for derivative panels.
BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up
Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179365
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These need to be set before the kernel will work without
running the VBIOS option rom.
Also necessary is setting the PP_CONTROL register with
the EDP_FORCE_VDD bit.
BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up
Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add XDR functions and use them to convert the ELF headers
to native headers, using the Elf64 structs to ensure we accomodate
all word sizes. Also, use these XDR functions for output.
This may seem overly complex but it turned out to be much the easiest
way to do this. Note that the basic elf parsing function
in cbfs-mkstage.c now works over all ELF files, for all architectures,
endian, and word size combinations. At the same time, the basic elf parsing
in cbfs-mkstage.c is a loop that has no architecture-specific conditionals.
Add -g to the LDFLAGS while we're here. It's on the CFLAGS so there is no
harm done.
BUG=None
TEST=Build and boot for Peppy; works fine. Build and boot for nyan, works fine. Build for qemu targets and armv8 targets.
BRANCH=None
Change-Id: I5a4cee9854799189115ac701e22efc406a8d902f
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178606
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Patch 547fbbfe2e introduced an off-by-one error in the offsets of the
PMU register struct, which put both the newly added register and the
PSHOLD that comes after it in the wrong place. This patch corrects the
offsets (5420 had already been correct).
BUG=None
TEST=Boots on Snow.
Change-Id: I1d9d31a6a73ee91890824e94fbd247d5feb4f6ae
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179411
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
On Tegra1x4 platforms, certain display-related registers
cannot be accessed unless the VPR registers are correctly
set up first. This allows the kernel graphics driver to
talk to the HW in the same manner on all Tegra SoCs.
Change-Id: I96e0c4075709da51be530a473da8d593ca498722
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/179327
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Now that the SD card controller is limited to the SD card
2.0 spec it's possible to use 20K pulls for the pads.
BUG=chrome-os-partner:24423
BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without
any errors.
Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179423
The rambi board can only meet the SD card 2.0 specification.
Therefore, the controller capabilities need to be overridden
to match.
BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows
high speed as maximum timing as well as 3.3V signal voltage.
Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179415
The SD card controller can have the capabilities it supports
to be overridden. Add two optional fields to the chip structure
to allow the mainboard to override the SD card controller
capabilities.
BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. Noted capabilities override console output.
Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The VDAT data was off by 2 bytes when reading it from the
kernel. The reason is that the header did not line up
correctly with actual ACPI code.
BUG=chrome-os-partner:24440
BRANCH=None
TEST=crossystem devsw_cur now returns either 0 or 1 depending
on state.
Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a
Signed-off-by: Aaron durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179372
Bay Trail has 3 banks of gpios. Therefore, in order to
properly identify a gpio the specific bank number as well
as the GPIO within that bank is needed. The SPI
write-protect GPIO is GPIO 6 within the SUS bank (offset
0x2000).
BUG=chrome-os-partner:24324
BUG=chrome-os-partner:24408
BRANCH=None
TEST=Built and booted. Looked at GPIO sysfs in the
chromeos_acpi directory.
Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179195
The coreboot eclass can append these options to the coreboot config to enable
the serial console.
BUG=None
TEST=Built and booted on nyan and verified that serial was enabled. Built for
all other supported boards except baskingridge which is already broken.
BRANCH=None
Change-Id: I01cfce6dafc866bcc30d98f064a320f2243b4fed
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178210
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Install the BL1 and set up the checksum in the Makefile instead of relying on
post processing. Import the exynos checksum script, split it in two and
simplify it significantly. Stop putting the CBFS header in the midst of the
bootblock so that it can be checksummed before CBFS is put together. Stop
saving space for it and leaving an anchor in the bootblock which nobody looks
for.
BUG=None
TEST=Built and booted on pit. Built for snow, but it doesn't boot on ToT so I
couldn't test it more than that.
BRANCH=None
Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/179229
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The LPE audio device needs 1MiB of memory for its firmware.
It also has a requirement that the memory needs to be on a
512MiB boundary. Just take 1MiB @ 512MiB for the LPE device.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and analyzed console logs for resources. Also interrogated
registres within the kernel.
Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b
Reviewed-on: https://chromium-review.googlesource.com/179192
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
The test on official ChromeOS firmware bitmaps will be very blurry if
the screen resolution is too low (current value, 0x114 = 800x600).
BUG=chrome-os-partner:23766
TEST=emerge-panther chromeos-coreboot-panther
Change-Id: I0b26a3d4a14397fb7e195cda57bc5c1bc713e29e
Signed-off-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179202
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the
default input GPIO type MMIO.
BUG=chrome-os-partner:24408
TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat
/sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic
jack status.
BRANCH=None
Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179169
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up
on certain boards.
BUG=chrome-os-partner:24353
TEST=Manual. Burn FW on board that previously failed to boot eMMC,
verify chromeos can now install + boot from eMMC.
BRANCH=none
Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rambi 1.5 boards use the native SD card controller on baytrail.
Therefore, enable those signals. The CLK, D*, and CMD pins use
2K pulls as these were shown to not exhibit any errors when
doing reads or writes to a DDR50 sd card.
Note that if a servo is connected on needs to enable the
sd_vref_sel rail to pp1800 as this causes issues with card
detect if it is not set to pp1800.
BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Tested sd card read and write works in kernel.
Also noted that write protect detection works as well.
Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178961
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The enable_resources callback was accidentally populated
with NULL. Make that callback be the generic
pci_dev_enable_resources.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted.
Change-Id: I670b51bd9aff6764e9b549287a737b662572cdc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178960
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The USB VBUS GPIOs on Nyan boards are two-directional: usually the SoC
sets them high or low to enable USB power, but on overcurrent conditions
they get forcefully driven low by the voltage source. To avoid driving
it from two sides, we configure them on the SoC side as tristated input
pins with a pull-up instead.
BUG=None
TEST=Made sure USB devices still get detected.
Change-Id: I423cb312805cbacb651a569ddc1530813b148576
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178914
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
The new IASL is complaining about the PCI memory region not
having consistent base/end/length values because they are
placeholder that are fixed up in the method before returning.
Put in some more valid placeholder values to make it happy.
BUG=chromium:311294
BRANCH=none
TEST=build and boot with IASL 20130117 on rambi
Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178864
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@google.com>
Rambi has the LPE audio codec connected to PMC_PLT_CLK[0].
Configure it for 25MHz.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Noted message in console output.
Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178781
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Add device tree option to determine if the LPE
audio codec has a platform clock signal connected
to it from the SoC. If a frequency is selected the
platform clock number is used to enable the
clock.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted rambi with 25MHz option. Probed pin
to audio codec. Noted 25MHz clock.
Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178780
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The C standard considers it legal to return a NULL pointer for zero
length memory allocations, and our malloc implementation does in fact
make use of that. xmalloc() and xzmalloc() should therefore not consider
this case a failure.
Also fixed a minor formatting issue.
BUG=None
TEST=Made sure xmalloc(0) and xmalloc(1000) succeed and
xmalloc(0xffffffff) still dies.
Change-Id: Ib9b75df9458ce2ba75fd0bc0af9814a3323298eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178725
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
There are 3 banks of GPIOs that need to be described
with specific _UID and memory/interrupt values.
BUG=chrome-os-partner:24314
BRANCH=none
TEST=build and boot on rambi, check for probed driver:
gpiochip_find_base: found new base at 154
gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00
gpiochip_find_base: found new base at 126
gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01
gpiochip_find_base: found new base at 82
gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02
fed0c000-fed0cfff : INT33FC:00
fed0c000-fed0cfff : INT33FC:00
fed0d000-fed0dfff : INT33FC:01
fed0d000-fed0dfff : INT33FC:01
fed0e000-fed0efff : INT33FC:02
fed0e000-fed0efff : INT33FC:02
Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178601
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These panel numbers provided by the OEM.
The old display will stop working.
BUG=None
TEST=builds. I'll test when I get a unit.
BRANCH=None
Change-Id: I6020f0c725d44c4b69d5806e0dfc8da125686baf
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177958
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
The xmalloc wrapper checks whether the malloc succeeded, and if not stops
execution and prints a message. xmalloc always returns a valid pointer. The
xzalloc wrapper does the same thing, but also zeroes the memory before
returning it.
BUG=None
TEST=Used this function in nyan, built and booted on it.
BRANCH=None
Change-Id: I00e7de04a5c368ab3603530b98bd3e3596e10632
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178001
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi, check that C1/C2/C3 are all used now
Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178461
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Some 1.5 boards have a single channel ram configuration.
Accomodate such configs.
BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built and booted ChromeOS.
Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178340
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
