Including the Virtual Button Driver made laptops report as a detachable
in tablet mode. Adjust how it's included, so they report as laptops.
Change-Id: Idc2076c400524744836e2f52124ccb8502622b04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the board type to ULX as seen in the AMI CRB. This fixes
failed memory training for certain memory modules.
Change-Id: I951387fcfc0be8fb931b4c5ac0b5f022e057b371
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are not referenced anywhere, so remove them.
Change-Id: Ieb66099dcb9e13b26e6a7a752584537c060c8c18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86317
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorder the PCIe reset before mtk_dram_init to overlap the de-assert
time with the DRAM initialization process. This change helps to optimize
the initialization sequence and reduce overall boot time.
BRANCH=rauru
TEST=Build pass
BUG=b:391333055
Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit sets the TCC offset for the Fatcat baseboard variant.
A value of 10 was chosen, resulting in a TCC trip point of 100C
(Tjmax of 110C - offset of 10C).
This allows for thermal throttling to begin at a more appropriate
temperature.
Fatcat variants can override the TCC offset as per platform
requirements between power and/or performance.
TEST=Able to build and boot to CrOS.
Change-Id: I2a57fd3b06378f4e62872ffeb116a65561100e33
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86292
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
H9JCNNNCP3MLYR-N6E 3 (0011)
BUG=b:394756067
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I9945ef9f8b9f5de8aedc34e4bc41c29a702be819
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for minimum/maximum limit values as well as
step sizes for CFR number options. Additionally, add a new flag that
specifies the option should be displayed in hexadecimal notation instead
of decimal.
Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implements a way for CFR options to depend on another option
being set to one or more specific values. This is achieved
by writing a list of values as a varbinary struct.
Change-Id: Iaf7965551490969052eb27c207fa524470d4dd6a
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a version field to the CFR root struct so parsers can check
compatibility when parsing structs.
Change-Id: Ifcb950f1bdedc0ab925f3841befb7e7001c0f7f4
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Linux complains in dmesg as a firmware bug that BSP is not the first
entry.
NetBSD hangs and OpenBSD panics early on boot.
With this patch I was able to boot NetBSD and OpenBSD on darp10-b when
loaded in GRUB.
Note: vanilla bootloaders for NetBSD and OpenBSD still result in an
apparent hang for an unknown reason.
Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Pull HPD (Hot Plug Detect) pin up in order to detect the panel.
BRANCH=rauru
BUG=b:376357839
TEST=Verify FW screen on Navi and Hylia
Change-Id: Ie11ceabad0b9872729125936d90b93b5d6d7cea6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86294
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Rauru follower device goes `load switch` path to ensure the
discharge timing meets the panel power-off sequence. Refactor panel.c to
support this hardware change.
Remove PANEL from fw_config since this is a board-specific change.
BRANCH=rauru
BUG=b:339580836
TEST=verify firmware screen on Navi
Change-Id: I57dcaa2a0b5af94fe3fa3eaf04e9f3159c51d144
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Previously, the lid switch could be set to not wake the system.
Add another option to ignore the switch entirely.
Change-Id: I1dd666a44b332ffbbef4420799eeffd746fd1664
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86305
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option alongside the three existing curves to just turn
off the fan.
Change-Id: I39f6599056fe0116abbd7e2eb4084f77a7c395d3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add rcomp configuration values taken from the AMI CRB. This fixes
failed memory training for certain memory modules.
Change-Id: If7a29bbd015d45eac178480ba6cae42912e25195
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The DDR5 modules have a speed size of 1024 bytes, not 512. Update
Kconfig to reflect this.
Change-Id: Ic7b691104ff8b0061a485f01709a2f53046cc94a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
To resolve the issue of not being able to boot from USB on Francka, the USB PHY settings need to be modified.
BUG=b:394206896
TEST=Build and test Type-A port function works fine
Change-Id: I140b8a2047768d3aeb0d5919aad998bd9dcd099f
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Update sagv gears and frequency values as per recommendation
from power and performance team.
BUG=none
TEST=Boot to OS.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I315fcac387680df9312880120b7e6d33bded38e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
MAILBOXES_DESKTOP is unused, and the IGD opregion spec makes no
distinction in the mailboxes supported between desktop and mobile
platforms. Rename MAILBOXES_MOBILE to IGD_MAILBOXES for consistency
with other mailbox variables and clean up the comment.
Change-Id: Ia06fe75702887aa6953bf17bd4bc14af4038bec5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86279
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IGD mailbox #2, Software SCI Interface, is not supported by coreboot
currently, as it requires supporting the Get BIOS Data (GBDA) and
System BIOS Callbacks (SBCB) interfaces. Since coreboot doesn't
support these, don't advertise mailbox #2 support.
This eliminates an error with the Linux display drivers:
"SWSCI request timed out"
TEST=build/boot Linux 6.9, Win11 on starlabs/starlite_adl
Change-Id: I8efcf9c5d384b6e0ce159d65cb1497c2e2e47f42
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86276
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Intel's reference implementation in Slimbootloader pads the area
allocated for the extended VBT to the nearest 512-byte boundary, which
strongly suggests that the Windows driver expects the same.
TEST=build/boot Linux 6.9, Win11 on starlabs/starlite_adl, verify
VBT read properly by OS.
Change-Id: Ib3784eea6eb929ffec9672fc123b833c11c057e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86275
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This has no noticable affect apart from being more consistant with
other boards.
Change-Id: Ia2d9284a7dfd29f47356860d6085c7aa5b94adb4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86289
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The schematics show that these are not connected, so disconnect
the GPIOs and set the ports to OC_SKIP.
Change-Id: I9e2b087b348fbae12edaf085fb61776277514c93
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
DEEP proves more reliable on Linux with USB-C displays.
Change-Id: I04e243c6409af64fef0996b474aa448ce32b2da9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86287
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The schematics show this pin isn't connected, so disconnect it.
Change-Id: Ib21048fa0972231410b7e8f7829a9eeac1d065c7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Otherwise flags field is pre-filled with random garbage.
Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This prevents Windows from displaying the IOM device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify IOM device
not shown as unknown device in Device Manager.
Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86257
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This prevents Windows from displaying the PMC device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify PMC device
not shown as unknown device in Device Manager.
Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This is not connected, so update the configuration to
reflect that.
Change-Id: I2922988758e0fa73b4d29ac13380f20f4606cd8e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This causes FSP-M to fail memory training, so disable it.
Change-Id: I4a3544a153d6d4da95c4d679665d9c92bd04ed87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86268
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not use CNVi, so disconnect the unused GPIOs.
Change-Id: I93457ed65e11c9f6f3bff052bb0d82a0389b67c9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The upstream arm-trusted-firmware has removed the DISABLE_PEDANTIC
option in Commit 79eb1aff7850 ("Remove DISABLE_PEDANTIC build option").
Therefore, drop the option for BL31.
Change-Id: Iaca07ce190c566fe79814fd8bbd8821d3ea76955
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Rectify board configuration flags based on the schematics Doc.
105-D99700-00C and User Guide #58168 (NDA).
Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85493
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All 16 IVB PCIe lanes go to one x16 slot without bifurcation.
There is no use for peg11.
Hide it to squelch the leftover devices warning.
Change-Id: I75402d338e64f477f40682f796477e8fcb94a4e8
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hide peg12, dev4, and peg60 devices to squelch leftover devices
warning seen with p8z77-m, p8z77-v and p8z77-v_le_plus:
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:00:01.1
[WARN ] PCI: 00:00:01.2
[WARN ] PCI: 00:00:04.0
[WARN ] PCI: 00:00:06.0
[WARN ] PCI: Check your devicetree.cb.
No board in this family can do the 8/4/4 PCIe lane split to
require the peg12 bridge, or implemented dev4 at all.
Only p8c_ws wired up the 4 extra Xeon PCIe lanes peg60 is supposed
to cover, and its overridetree already enables it.
Therefore, be proactive and hide these from the rest of the family.
Change-Id: I24234e6b77a9effc577c8e22c77bb9896b983b7f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
