The ASPM option for CPU root ports was guarded against the
SOC supporting CPU root ports. This meant that the option
was visible for boards that didn't utilise the CPU root
ports.
Adjust this to guard against BOARD_STARLABS_STARBOOK_RPL,
which is the only board to actually use the CPU root ports.
Change-Id: Id632a8279e8c1cb07536b4198c3752d57eee657a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89908
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the code that disables the DMIC based on the option table
to the common directory, as it's pretty much the same for all
boards.
Drop the check for the codec ID, as it's pointless.
Change-Id: I55dd8f5f65908f5c4605001893003209f85cb139
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Split the "wireless" option into "WiFi" and "Bluetooth" in CFR
to allow more granular control.
Test=Disable WiFi and Bluetooth in turn and make sure the devices
are disabled independently.
Change-Id: I3f617486c78a89a60a1e8c7c8ab7d157dc20bf2e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89797
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the wireless CFR object to allow users to disable or
enable the built-in wireless.
Change-Id: I8f48bf30429d64980d15d33f9e26164e806c520c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89810
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all of the CFR object definitons to the common directory
to reduce duplicated code.
Change-Id: I02d486563a01738335a9f1a20b5fcad2b96d6498
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89809
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust how the common headers are included, in a more "coreboot"
fashion.
Change-Id: Iaeb8e12272235a51c620656387838be8b0a0a098
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89917
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the new memory CXMT CXDB5CBAM-MA-B.
BUG=b:451917928
BRANCH=firmware-dedede-13606.B
TEST=Run command
"go run ./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
And confirm the mainboard boot normally with CXMT
CXDB5CBAM-MA-B memory.
Change-Id: I8e1600ac191fd76b2226605e7a72497823a48105
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add the ability to set the keyboard backlight level at boot, controlled
by a setup option variable and restricted to devices which actually
have a backlit keyboard.
TEST=tested hooked up to a CFR option 'ec_kb_backlight' (added later in
the patch series) to set the keyboard backlight at boot, with
visibility controlled by backlight presence, on a range of Chromebooks
with and without keyboard backlight support.
Change-Id: I92eed62935d0333f548599860b7bbe22f6b9f2b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89828
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reduce maximum timeout from 100ms to 20ms for OTG Enablement polling
for USB Type-C.
Avoid OTG enablement polling when in sink mode
BUG=b:455551151
TEST: Verify USB3.0 (SS) works for C0/C1 on Google/Bluey.
Background:
During USB Type-C port initialization, the OTG (On-The-Go) status must
be verified when the port operates in source mode to ensure proper VBUS
power delivery. The previous implementation polled the OTG status
register with a 100ms timeout on all ports regardless of their role.
Previous Implementation Issues:
1. Overly conservative timeout: The 100ms maximum wait significantly
exceeded actual requirements, as OTG enablement consistently
completes in approximately 14ms under normal conditions
2. Inefficient polling logic: OTG status was polled even when ports
operated in sink mode, where OTG functionality is irrelevant since
the port receives rather than provides power
Improvements:
1. Timeout reduction: Decreased maximum polling duration from 100ms to
20ms, maintaining adequate margin (>40% headroom) while reducing boot
time by up to 80ms per sink-mode port
2. Mode-aware polling: Added logic to detect port role and skip OTG
status polling entirely for sink-mode ports, as demonstrated by the
"Primary in SNK mode - skipping OTG status read" log entry
The changes maintain full USB3.0 SuperSpeed functionality while
improving initialization efficiency. The 20ms timeout remains
sufficiently conservative to accommodate normal timing variations.
Debug logs:
[DEBUG] QMP PHY SS0 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Primary VBUS SuperSpeed
[INFO ] Primary in SNK mode - skipping OTG status read
[INFO ] Primary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x1a
[INFO ] Src Status (0x2B08): 0x00
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0x02
[DEBUG] USB HS PHY initialized for index 3
[DEBUG] QMP-1x16 USB4 DP PHY SS1 init
[DEBUG] QMP PHY SS1 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Secondary VBUS SuperSpeed
[INFO ] Secondary in SRC mode - OTG Status: 0x02, State: 0x02
(OTG Enabled) - Time: 14 ms
[INFO ] Secondary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x4b
[INFO ] Src Status (0x2B08): 0x08
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0xa6
confirmed that there are no otg polling for sink mode and
polling timeout is reduced to max of 20ms.
Change-Id: I7467248185c9d0526816ac62e1e1a1496440fddc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This reverts commit 668ea97075.
Let's just keep using --param=min-pagesize=1024 in xcompile to sweep
the -Warray-bounds warnings under the rug in the coreboot tree.
Change-Id: I0f76c27bcbaac9d0927160fcab9cbf9aaefa9095
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89915
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit cfdaff3f70.
Let's just keep using --param=min-pagesize=1024 in xcompile to sweep
the -Warray-bounds warnings under the rug in the coreboot tree.
Change-Id: I875cb140aacd44f1aaddd410de0f154af585b1c1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix multiple critical thermal management problems while preserving the
quiet-at-idle design:
- Overlapping temperature thresholds causing fan oscillations
- CRITICAL_TEMPERATURE equal to Tj_max (no safety margin)
- Multiple fan levels trying to activate simultaneously
Issues fixed:
1. CRITICAL_TEMPERATURE: 100°C → 98°C
- Was equal to Tj_max, leaving zero safety margin
- System could reach absolute thermal limits before shutdown
- 2°C margin allows clean shutdown before CPU thermal protection
2. Fix overlapping temperature thresholds (PRIMARY BUG)
- Previous config had all fan levels overlapping:
* FAN3: 48-55°C
* FAN2: 52-64°C (started at 52°C, before FAN3 stopped at 55°C)
* FAN1: 60-68°C (started at 60°C, before FAN2 stopped at 64°C)
* FAN0: 66-78°C (started at 66°C, before FAN1 stopped at 68°C)
- Multiple fan levels would try to activate simultaneously
- Caused rapid fan speed oscillations and unpredictable behavior
New configuration with proper discrete levels:
* FAN3: 45-55°C
* FAN2: 55-65°C (starts when FAN3 stops)
* FAN1: 65-72°C (starts when FAN2 stops)
* FAN0: 72-80°C (starts when FAN1 stops)
3. Increase PWM values for better cooling at each level:
- FAN3: 0x40 → 0xA0
- FAN2: 0x80 → 0xB0
- FAN1: 0xb0 → 0xC0
- Provides more effective cooling progression
Design philosophy:
- Keep FAN4_PWM = 0x00 (fan OFF at idle)
* Chromebox designed as quiet desktop device
* Passive cooling adequate below 55°C
* Silent operation at idle/light loads
Configuration now follows best practices:
- Silent at idle (fan OFF until >45-55°C)
- No overlapping thresholds (discrete fan levels)
- 8-10°C hysteresis (prevents oscillation)
- Proper safety margin below Tj_max
- Progressive PWM values for smooth transitions
These changes fix the actual bugs (overlaps and safety margins) while
maintaining the intended quiet operation at idle.
TEST=build/boot stumpy, verify fan remains silent at idle, activates
smoothly when needed, no oscillations, proper cooling maintained under
load.
Change-Id: I284cbe34348345589564ae77828b9beee0b0d9c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Fix thermal management issues across Jecht variants.
tidus (CRITICAL):
- PASSIVE_TEMPERATURE: 105°C → 95°C
* Was higher than CRITICAL_TEMPERATURE (103°C)
* OS would initiate emergency shutdown before CPU throttling
* Passive CPU throttling would NEVER engage
* Now activates at 95°C, well before critical shutdown at 103°C
guado:
- Fix threshold spacing and eliminate minor overlap
* Old: FAN1:65-70, FAN0:90-100 (with FAN2 stopping at 67°C)
* Had 2°C overlap between FAN1 and FAN2
- Standardize thresholds: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
- Adjust PWM values for consistent progression
* FAN3: 0x55→0x62, FAN2: 0xa6→0x86, FAN1: 0xc0→0xa8, FAN0: 0xff→0xdc
* More linear progression, better acoustic profile
rikku:
- Improve hysteresis (was only 5°C, can cause rapid switching)
* Old: FAN3:42-47, FAN2:54-59, FAN1:66-71, FAN0:78-83
* New: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
* 8-12°C hysteresis prevents oscillation under varying loads
- Adjust PWM values for smoother progression
* Old progression was too aggressive (0xa5, 0xb2, 0xc9, 0xd8)
* New: 0x62, 0x86, 0xa8, 0xdc (more gradual)
All three variants now properly configured for Broadwell with
Tj_max=105°C:
- tidus: Critical passive cooling logic fixed
- guado/rikku: Aligned with jecht reference configuration
- No overlapping thresholds
- Proper hysteresis for stable operation
- Consistent PWM progression across variants
Note: jecht variant was already properly configured and serves as the
reference implementation for this thermal pattern.
TEST=build/boot Win10/Linux on google/guado, verify fan speeds work as
expected when varying the CPU load/temp.
Change-Id: I0502829665f373215e6be9aaf1c082abe0b613fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Fix critical thermal management problems across all Beltino variants
while preserving the quiet-at-idle design intent:
- Overlapping temperature thresholds causing fan oscillations
- CRITICAL_TEMPERATURE equal to Tj_max (no safety margin)
- Poor threshold spacing creating thermal management gaps
Variant-specific fixes:
panther (CRITICAL SAFETY ISSUE):
- CRITICAL_TEMPERATURE: 100°C → 98°C
* Was equal to Tj_max, leaving zero safety margin
* System could reach thermal limits before clean shutdown
* Risk of hardware damage
- Reorganize thresholds: eliminate 25°C gap between levels
* Old: FAN3:40-50, FAN2:75-83 (25°C gap!), FAN1:86-90, FAN0:93-96
* New: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
* Progressive response instead of sudden jumps
- Adjust PWM values for smoother progression
zako (SEVERE OPERATIONAL ISSUE):
- Fix catastrophic overlapping thresholds
* All 4 active fan levels tried to activate simultaneously (50-52°C)
* Old: FAN3:48-52, FAN2:50-55, FAN1:52-58, FAN0:55-60
* Fan would oscillate wildly between speeds
- New: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
* Proper discrete levels with no overlaps
* 8-12°C hysteresis prevents oscillation
monroe:
- Fix overlapping thresholds across all levels
* Old: FAN3:45-58, FAN2:52-64, FAN1:59-68, FAN0:66-79
* FAN2 started before FAN3 stopped, same for FAN1/FAN0
- New: Clean discrete levels with proper spacing
mccloud:
- Raise FAN3 start: 35-40°C → 40-50°C
* 35°C is barely above ambient, causes unnecessary noise
- Standardize remaining thresholds to match other variants
tricky:
- Already had reasonable thresholds, no changes needed
Design philosophy:
- Keep FAN4_PWM = 0x00 (fan OFF at idle)
* Chromeboxes are designed as quiet desktop devices
* Passive cooling adequate below 50°C
* Silent operation at idle/light loads
* Fan only activates when thermal load requires it (>40-50°C)
All variants now follow proper thermal management:
- Silent at idle (fan OFF until >40-50°C)
- Progressive thresholds: 40-50, 55-67, 67-75, 85-90°C
- No overlapping ranges (discrete fan levels)
- 8-12°C hysteresis (prevents oscillation)
- 2°C safety margin below Tj_max for critical shutdown
These changes fix the actual bugs (overlaps and safety margins) while
respecting the original quiet-desktop design intent.
TEST=build/boot panther, verify fan remains silent at idle, activates
smoothly when needed, no oscillations, proper shutdown margin
maintained.
Change-Id: Ibcd138dfb16b13dfa2ef3a3fcac2556d7daaf0c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Remove unused GNVS fan thresholds, PWM assignments from acpi_tables.c.
The Beltino thermal.asl uses compile-time macros (FAN*_THRESHOLD_OFF,
FAN*_THRESHOLD_ON, FAN*_PWM) directly from variant/thermal.h, not
runtime GNVS variables. The GNVS assignments were never consumed by
the ACPI code and just wasted memory.
Retained GNVS values that ARE used:
- tpmp: TPM presence flag
- tcrt: Critical temperature (\TCRT)
- tpsv: Passive temperature (\TPSV)
- tmax: Tj_max (\TMAX)
Removed unused GNVS values:
- f{0-4}{of,on,pw}: Fan thresholds and PWM values (24 values total)
- flvl: Fan level (unused, ACPI uses \FLVL local variable)
This matches the google/jecht approach which also uses compile-time
macros and only sets the essential GNVS thermal values.
No functional change - the ACPI thermal zone behavior is identical.
Change-Id: I703b7d8e424d4451abf0781b4491b813be216bc7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Document the ACPI thermal zone pattern used across multiple mainboards
that implement five-level fan control via power resource state machines.
This pattern is used by 9 mainboards including Google Chromebooks
(beltino, jecht variants), Samsung stumpy, and Intel reference boards
(wtm2, baskingridge, emeraldlake2).
The documentation covers:
- Power resource state machine implementation
- Temperature management via PECI/SuperIO
- Active and passive cooling policies
- Critical FNP4._OFF no-op requirement for Windows compatibility
- Implementation variations and checklist for new boards
Initial framework generated by Cursor AI, heavily edited thereafter.
Change-Id: I4174a4552c97fb85a894f5362948d57057cacb81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
It was accidently added and is just dead code.
It doesn't change any functionality.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I868b8c8725fc2240543fb1e9e379ecb5e1471ef4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89898
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Replace the memory-mapped LPSS UART2 with I/O port-mapped legacy
8250 UART for the serial console.
- Replace INTEL_LPSS_UART_FOR_CONSOLE with DRIVERS_UART_8250IO
- Add SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE to enable COM2
- Change UART_FOR_CONSOLE from 2 to 0 (COM1 at 0x3F8)
DRIVERS_UART_8250IO enables COM1 (I/O port 0x3F8).
SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE enables COM2 (I/O port 0x2F8).
TEST=Build and boot on mc_rpl1. Verify console output on both COM1
and COM2.
Change-Id: I93deaba5fedf8c9aecff4a425e8cec406d2759c2
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89892
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update EARLY_PCI_BRIDGE_FUNCTION from 0x0 to 0x2 for NC FPGA POST
code communication. This matches the PCI bridge function where the
NC FPGA is connected on this hardware.
TEST=Built and booted on mc_rpl1. Verified that POST codes display
correctly on the 7-segment display.
Change-Id: I52c463036091ac42c6db415d1d3e582e561aff67
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).
This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.
Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).
This enables proper fan control operation on Windows while maintaining
Linux compatibility.
TEST=build/boot Win10/Linux on samsung/stumpy, verify fan functional
under Windows 10, continues to work correctly under Linux.
Change-Id: I00431490ae080226d526c1e217bb10e8ded64c3c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89842
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).
This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.
Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).
This enables proper fan control operation on Windows while maintaining
Linux compatibility.
TEST=untested, but same as tested change on other mainboards in series.
Change-Id: I5d6c5f6cb8232b956bbd1be6220b8bb09c32b480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).
This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.
Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).
This enables proper fan control operation on Windows while maintaining
Linux compatibility.
TEST=build/boot Win10/Linux on google/jecht, verify fan functional
under Windows 10, continues to work correctly under Linux.
Change-Id: Iac60a18dd1e4b632d85384ddbbcfcddaf0b8d2cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).
This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.
Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).
This enables proper fan control operation on Windows while maintaining
Linux compatibility.
TEST=build/boot Win10/Linux on google/beltino, verify fan functional
under Windows 10, continues to work correctly under Linux.
Change-Id: Ie53ad9b547b2f2d522e2ed692f8db55aa9a6b8d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89839
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option existed to enable the MMIO eMMC DXE driver for AMD Picasso
boards with eMMC storage. The driver has been integrated into edk2 and
no longer requires guarding via a build-time option.
Remove the EDK2_PCO_MMIO_EMMC Kconfig symbol definition, associated
build logic, and the board-level select from google/zork.
TEST=build/boot AMD Picasso boards with edk2 payload.
Change-Id: I458a45ad752d88cc9252f2d8fe6b0e8ec054329d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This option existed because the inclusion of the UFS driver in edk2
needed to be guarded due to some issues on non-UFS equipped devices.
Those issues have been resolved in edk2, so the UFS driver does not
need guarding anymore.
Remove the EDK2_UFS_ENABLE Kconfig symbol definition, associated build
logic, and selection from google/brya baseboard.
TEST=build/boot UFS and non-UFS ChromeOS boards with edk2 payload.
Change-Id: I3f20d503de4a642ee3fbb175c267e1f5f7328c8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89857
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the default MrChromebox branch to uefipayload_2508.
This branch is rebased on the latest upstream edk tag
'edk2-stable202508', and includes a number of other improvements,
including memory safety fixes, improved support for eMMC on AMD
Picasso-based devices, improved UFS support for Alderlake-N based
devices, and a new driver supporting devices which use a Genesys
Logic GL97xx PCIe eMMC or SD card controller.
Change-Id: Id5d02da6396ce7ec7bfb7aaa90ebb234ec05020b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89856
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit adds a new Kconfig option to the `fatcat`
mainboard to enable VGA mode 12 support for early Sign of Life
(eSOL).
- This option, `FATCAT_VGA_MODE12_SUPPORT`, is dependent on
`FSP_UGOP_EARLY_SIGN_OF_LIFE`.
- It selects `ROMSTAGE_VGA` and `FSP_VGA_MODE12` to enable the
necessary VGA components.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: I3b9a433c7b3938b8cc17f44552b8463ee049e5c3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89092
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements the configuration of VGA mode 12 in the
Intel Pantherlake SoC's romstage. It integrates the newly added
text rendering API to display user messages using a planar buffer
instead of the standard VGA message string.
The changes include:
- A call to `render_text_to_bitmap_buffer()` to draw the message
on the bitmap buffer.
- Determining the display orientation from the common SoC
configuration, with an override for a closed lid.
- Calculating and setting the correct position of the rendered
text in the VGA buffer.
- Duplicating the single-plane bitmap data to all required planes
for VGA mode 12.
- Setting the `VGA_INIT_CONTROL_MODE12` bit in the FSP-M UPD
to inform FSP to use the new mode.
- Implementing the `soc_set_vga_mode12_buffer()` API to set the
corresponding FSP-M UPD for VGA mode12 buffer address.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Ic69fff0479020a31c7e6f0c52b4bdb25b1483bb9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds new Kconfig options and a code snippet to support
VGA mode 12 within the FSP (Firmware Support Package) 2.0. The
changes allow platforms to select VGA mode 12 and configure it.
The key features are:
- Introduces `FSP_VGA_MODE12` to enable VGA mode 12 support.
- A new `FSP_VGA_MODE12_BPP` option defines the bits per pixel,
defaulting to 4 for color mode.
- A bitmap buffer is allocated on the stack and supplied to FSP
based on the configured bits per pixel.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Iaa3a64b7c8c735d8329b3596f4be315871bc7fa4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add 2 new timestamps for measuring the time to generate pKVM
deterministic random number generator seed in depthcharge.
First indicate when the generation has started and
a second when the setup is complete.
BUG=b:449097147
TEST=builds
Change-Id: I1bced5a331e4d10a1ec1c305b9b2a41d1e913579
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89872
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch fixes a number of rare edge cases in handling the precision
argument in printf. The existing printf implementation used 0 as the
sentinel value for "no precision provided", which makes sense for
integers (where 0 precision has the same effect as no precision, since
in both cases no extra zeroes will be added to the front). However, for
strings it can make an important difference, since callers may expect
that they can use `printf("%.*s", len, str)` to guarantee that `str`
doesn't get dereferenced when `len` is 0. Therefore, change the
implementation so that negative values are used to represent "no
precision provided", and 0 is a legitimate value.
print_string() also had the problem that it called strlen() on the
string before even evaluating the precision. That of course defeats the
purpose of the common "%.*s" pattern to access unterminated strings.
This patch fixes the problem.
Finally, this patch slightly modifies the behavior when printing a NULL
pointer as a string, to make sure width and precision values are still
taken into account in that case, and to change from `(NULL)` to `(null)`
to match the behavior in glibc.
Change-Id: I787c18e1d33006842cf758aeb87710f80f0e5a40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89837
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable hardware-managed microphone privacy by setting the
PchHdaMicPrivacyMode FSP UPD to 1. This feature was enabled by
default in FSP previously but has since changed to disabled by
default, so now coreboot explicitly enables this as it is a desired
feature for Chrome platforms.
The hardware-managed microphone privacy feature allows the platform
to control the microphone mute state at the hardware level for
enhanced privacy.
TEST=Verify UPD value is set correctly and HW managed mic privacy is
working as expected.
Change-Id: I9a20bd129103aae35550104f6a7025484ef5e9c1
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88451
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Modify touchpad device setting to enable the ELAN touchpad.
schematics: RUBY_EVT_0902_2112.pdf
Device i2c log:
[INFO ] \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ] \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
[INFO ] \_SB.PCI0.I2C0.D04B: TI SPK AMP L at I2C: 00:4b
[INFO ] \_SB.PCI0.I2C0.D04C: TI SPK AMP R at I2C: 00:4c
[INFO ] \_SB.PCI0.I2C0.D04D: TI SPK AMP TL at I2C: 00:4d
[INFO ] \_SB.PCI0.I2C0.D04F: T1 SPK AMP TR at I2C: 00:4f
[INFO ] \_SB.PCI0.I2C3.TPMI: I2C TPM at I2C: 00:50
[INFO ] \_SB.PCI0.I2C4.H015: ELAN Touchpad at I2C: 00:15
[INFO ] \_SB.PCI0.I2C5.H014: Goodix Touchscreen at I2C: 00:14
[INFO ] \_SB.PCI0.RP01: Enable RTD3 for PCI: 00:00:1c.0 (Intel PCIe Runtime D3)
Changes:
hid : From PIXA2305 to ELAN2705
hid_desc_reg_offset : From 0x20 to 0x01
address : From 0x2C to 0x15
BUG=b:449901218
TEST=Build and boot to OS and use Elan touchpad module to verify the cursor works.
Change-Id: I11dcca5db5558af4cdd4b87a9b42519615839fef
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit removes the explicit CONFIG_HAVE_BMP_LOGO_COMPRESS_LZMA
definition from the Panther Lake Kconfig.
This local Kconfig setting, previously defaulted to 'n', is redundant
because the Panther Lake build now correctly inherits the intended
system-wide default, which is to use LZMA compression for the BMP
splash screen.
Removing this unnecessary Kconfig option simplifies the configuration
and results in a measured ~3ms reduction in boot time during the
firmware splash screen rendering phase on Panther Lake platforms.
w/o this patch:
```
963:returning from FspMultiPhaseSiInit 1,096,797 (102,937)
17:starting LZ4 decompress (ignore for x86) 1,111,606 (14,808)
18:finished LZ4 decompress (ignore for x86) 1,111,641 (34)
17:starting LZ4 decompress (ignore for x86) 1,119,857 (8,216)
18:finished LZ4 decompress (ignore for x86) 1,119,879 (21)
```
w/ this patch
```
963:returning from FspMultiPhaseSiInit 1,097,817 (103,211)
15:starting LZMA decompress (ignore for x86) 1,110,058 (12,241)
16:finished LZMA decompress (ignore for x86) 1,111,096 (1,037)
15:starting LZMA decompress (ignore for x86) 1,117,554 (6,458)
16:finished LZMA decompress (ignore for x86) 1,117,906 (352)
```
Change-Id: I64579e53c7f307d1430767da04a413f80016487f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Use defined constants from ec.h instead of hardcoded integer values
in all CFR enum definitions for improved readability and
maintainability.
Change-Id: I13b313d0c7a177fc689c3022256eb17125354599
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89881
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the "wireless" option enable or disable the USB Bluetooth along
with the wireless card.
Change-Id: I253b83ac3efb768e91dba424be4cec6a56bf53f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89798
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For reasons currently unknown, using a level triggered interrupt for the
PS2 keyboard causes an IRQ storm under Windows when any key is pressed,
leading to audio distortion/dropouts. Work around this by using an edge
triggered interrupt instead.
BUG=none
TEST=build/boot Win11, Linux on google/skyrim (frostflow), verify kb
functionality, verify no IRQ storm or audio stutter/distortion under
Windows.
Change-Id: I6de426c5780b2f05571415e8e411e379de45b5bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
When the mainboard is Bluey, the Kconfig options 'ARM64_HAS_SECURE_OS'
and 'ARM64_HAS_SECURE_OS_PAYLOAD' are selected to pack and load the
QTEE firmware as a CBFS payload type, since its memory regions are non-
contiguous across system IMEM and DDR.
TEST = Create an image.serial.bin incorporating QTEE firmware and
ensure it boots to OS on X1P42100.
Change-Id: Iaedfa25d574af8451a7bb9a4a35c557f4e09eee2
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89554
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a fw_config for touchscreen and non-touchscreen sku.
Based on the field to differentiat the touchscreen I2C port on/off
and GPIOs configuration.
BUG=none
TEST=Update the fw_config field and check the ap log:
ABSENCE = 0 ... without touchscreen i2c probing messages.
PRESENCE = 1 ... with touchscreen i2c probing messages.
Change-Id: I5f2cc0b0c37986240fbbeae3668ccc250748295d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89851
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
commit 668ea970 ("commonlib/endian: Silence GCC -Warray-bounds false
positives") added `#pragma GCC diagnostic ignored "-Warray-bounds"` but
forgot to restore the diagnostic state at the end of the file.
Change-Id: I41b38758ce862490777ede63ff92d95d6ba21521
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89867
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change applies the same fix as coreboot change CB:89605 to the
kinmen variant. Without this change, headset jack detection won't work.
The original change 752d49a4ff was:
"mb/google/fatcat/var/moonstone: Disable RT721 clock stop support"
RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".
BUG=b:435094908
TEST=After plugging a headset, audio output is switched to it.
Change-Id: I468d949e1249548348493c070b4955c012ef7b4e
Signed-off-by: Norman Bintang <normanbt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89784
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
