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mb/siemens/mc_rpl1: Set PCI bridge function for NC_FPGA

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Update EARLY_PCI_BRIDGE_FUNCTION from 0x0 to 0x2 for NC FPGA POST
code communication. This matches the PCI bridge function where the
NC FPGA is connected on this hardware.

TEST=Built and booted on mc_rpl1. Verified that POST codes display
correctly on the 7-segment display.

Change-Id: I52c463036091ac42c6db415d1d3e582e561aff67
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Kilian Krause 2025-11-03 17:38:22 +01:00 • committed by Matt DeVillier
commit 534fceb36a
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
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@ -24,7 +24,7 @@ config EARLY_PCI_BRIDGE_DEVICE
config EARLY_PCI_BRIDGE_FUNCTION
hex
depends on NC_FPGA_POST_CODE
default 0x0
default 0x2
config EARLY_PCI_MMIO_BASE
hex