The function tlcl2_get_capability() is only linked when Kconfig TPM2
is being selected. Add a guard to not include the SMBIOS code when
TPM2 isn't selected.
TEST=Can compile the fTPM driver when TPM2 isn't selected.
Change-Id: I9385f15fc71c021f9be2bfb874898f76fa71fee4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91775
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Downstream bridges share the same PCI device ID as the upstream
bridge but have no firmware mailbox. Sending commands to them
causes timeouts. Add a forward declaration of dtbt_device_ops
to detect and skip bridges whose parent is also a dTBT device.
Tested on thinkpad t480: The 5s timeout is now gone.
Change-Id: I96febb0e52e0ffbe52a237212b8f708a7b05c6d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Generate a signed UEFI capsule from the final coreboot ROM image using
EDK2 BaseTools.
When using an EDK2 payload and enabling DRIVERS_EFI_UPDATE_CAPSULES and
DRIVERS_EFI_GENERATE_CAPSULE, the build produces build/coreboot.cap once
the ROM is finalised (after all files were added to CBFS). The capsule
can also be generated explicitly with `make capsule`.
Move the capsule generation and certificate preparation into
payloads/external/edk2/Makefile, including generating the trusted root
certificate PCD include via BinToPcd.
Support capsule flows with an embedded FmpDxe driver by optionally
embedding FmpDxe.efi into generated capsules, and wiring the
embedded-driver Kconfig options through to the EDK2 payload build and
capsule generation.
Always set PersistAcrossReset on the capsule. Make InitiateReset
configurable (default off) because Linux rejects capsules with
InitiateReset when writing via /dev/efi_capsule_loader.
Use CONFIG_DRIVERS_EFI_MAIN_FW_VERSION for GenerateCapsule
--fw-version, but fall back to parsing a leading <major>.<minor> from
CONFIG_LOCALVERSION when it is left at 0. If
CONFIG_DRIVERS_EFI_MAIN_FW_LSV is 0, use the resolved firmware version.
Document capsule generation and embedded driver configuration.
Corresponding edk2 patches can be found at:
https://github.com/tianocore/edk2/pull/12053
Change-Id: I5f56b894d40ddb49f3158bb72f0143d0ebe9c34c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90862
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
fwupd shows the ESRT (UEFI System Resource Table) version as 0 when
DRIVERS_EFI_MAIN_FW_VERSION is left at the default. That makes it easy
to ship firmware with no meaningful ESRT version and forces maintainers
to duplicate versioning in multiple places.
If DRIVERS_EFI_MAIN_FW_VERSION is 0, parse a leading "<major>.<minor>"
from LOCALVERSION (ignoring non-digits before/after) and encode it as
(major << 16) | minor (e.g. "v26.01-rc1" -> 0x001A0001).
If DRIVERS_EFI_MAIN_FW_LSV is 0, default it to the effective firmware
version. This provides a sane, more secure default (prevents accidental
rollback to older versions) while still allowing platforms to override
LSV explicitly when rollback is desired.
Test=boot adl/horizon and check `fwupdmgr get-devices` shows a
version:
├─System Firmware:
│ Device ID: f48f261c7fc0724729b817bfd4e8340e3195a6bc
│ Current version: 26.3
Change-Id: I3f47ee7a38e79312532f4ed5d4516c57911f727e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90861
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Linux btintel driver requires DSM function 3 (DSM_SET_RESET_METHOD)
to be supported before it will use the ACPI _PRR/_RST reset path.
Without it, the driver falls back to GPIO or USB reset.
Add set_reset_method callback that returns success. coreboot only
supports WDISABLE2 (GPIO); the _RST method already implements the
toggle. Update the capability buffer (0x03 -> 0x0b) to advertise
function 3 support. Change RDLY default from 105 to 160 ms to match
the Linux driver.
Change-Id: I6a7c9289dcffbbbd769ab3fb4e59765d2fef7598
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91445
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 1f2408f573 ("console: Fix flushing for slow consoles") fixed a
typo related to some refactoring of the CBMEM fast code path. However,
this also seems to have indirectly broken the SPI flash console, causing
only the console header messages at the beginning of each stage to be
stored.
This is caused by multiple calls to flashconsole_tx_flush() without a
call to flashconsole_tx_byte() in between them. Data is accumulated in a
buffer during calls to flashconsole_tx_byte(), which is then written to
the flash during a flush. If no tx calls occur between flushes, the
second call will try to write data of length 0, which seems to cause
rdev_writeat() to return -1. This causes an early return, since the
return value of rdev_writeat() must match the data length in order for
the rest of the flashconsole_tx_flush to run. The flush function
contains a busy flag to prevent recursive calls to itself, and the early
return prevents it from being reset. Thus, the busy flag remains set for
the remainder of the stage, blocking all future flushes.
The multiple flushes occur because vprintk flushes console drivers after
the string has been sent, but flashconsole_tx_byte() also calls a flush
whenever a newline is encountered. Because of this, flushes are disabled
for the remainder of each stage after the first printk call containing a
newline is stored to the flash console. Although this newline check
could be omitted, flashconsole_tx_byte() also invokes a flush when its
data buffer is full, which shouldn't be avoided.
Prior to the mentioned commit, the incorrect logic happened to prevent
the flush in vprintk, preventing the double flush issue from occurring.
The mentioned commit inverted the logic, allowing the double flush to
occur.
Address this by returning early if len = 0. While we're here,
consolidate the early returns into a single check and change the busy
flag to a bool instead of an int.
TEST=Console messages are not missing in the flashconsole. Tested on the
Lenovo ThinkCentre M900 SFF.
Change-Id: Ic6c2418f04a687610df020df117f7be90b1724b9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Convert the hybrid graphics mux into a generic device and give it an
alias so that the driver can reference it by name.
Change-Id: Icbf6f298cab9e11acc9363daba68f9fbc613e79d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a new driver which enables basic TBT support for the Alpine Ridge,
Titan Ridge, and Maple Ridge discrete Thunderbolt controllers.
This driver will initially be used on the Lenovo T480/T480s and
System76 RPL-HX platform boards.
Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75286
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RV3028-C7 driver currently uses i2c_dev_read_at() and
i2c_dev_write_at() for block transfers when accessing RTC registers.
These block transfer functions are not universally supported across all
I2C/SMBus controller implementations in coreboot.
Specifically, the Intel i801 SMBus controller does not implement block
read/write operations, causing the RV3028-C7 driver to fail on platforms
using this controller due to missing transfer ops.
Replace block transfers with byte-by-byte operations
i2c_dev_readb_at() and i2c_dev_writeb_at(). These functions are
supported by i801.
TEST=Verified new SMBus functionality on mc_ehl8 (i801 controller).
Verified I2C functionality still works on mc_ehl2.
Used i2ctools from OS to read out registers 0x00-0x06 and confirmed
values match date/time set in coreboot.
Change-Id: I8a40ae14e62e3acf7c3904a8654c1d58fe4eb813
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91199
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the Sandybridge Lenovo devices are spending 25msec waiting
for ME to signal if RAM has been replaced. At the same time the RFID
I2C EEPROM needs to be locked, taking about 26msec.
By moving the locking to romstage the time spent waiting for ME can
be used to do something useful and thus reduce boot time.
TEST=On Lenovo X220 it boots 24msec faster.
Change-Id: Idd1f02a20dab6e422d55e3cf01d7b4a168792272
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The gpio-keys is a Linux-specific ACPI interface, and the kernel driver
does not care what the status is. Windows does not have drivers
however, so set the ACPI status to HIDDEN to avoid an unknown device
from appearing in Device Manager.
TEST=build/boot Win11 on google/magolor, verify PENH device no longer
listed under Device Manager.
Change-Id: I8a476e57b36c26795bfe9605e725ba3d5f860b3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91068
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use I2C block read command to access the VPD EEPROM to speed up
SMBIOS table generation, but keep the single byte read as fallback.
Shrink the size of the mainboard version string to not crossing the
128 byte block boundary.
TEST=On Lenovo X220 the BS_WRITE_TABLES is 15 msec faster.
Change-Id: Ida21a8dc653551440e79b062abcce9194d11bef4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91029
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Ensure that the mainboard version string is fully contained within
one 128byte block of the EEPROM. Since it's read from offset 0x27
it can be 89 characters long. One byte for the final null terminator.
Change-Id: I264ea2d1f634bb3493858da9f066bd6cef1ca960
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Generate an 'EMMC' ACPI device under the PCIe root port to which the
GL9763E is attached. The EMMC device contains a child CARD device whose
_RMV method returns 0. This allows Windows to identify the eMMC as a
fixed internal drive instead of a removable one.
This fixes an issue where the Windows 11 installer fails around 55%
with a generic 'Windows 11 installation has failed' error. Install
logs show the failure is due to Windows identifying the storage
device as removable and aborting (error 0xC1420134).
TEST=build/boot Win11 installer on google/taeko with eMMC installed,
verify Windows installer identifies it as a non-removable drive via
diskpart, and install completes successfully.
Change-Id: I51e59cb9e9dc2459724138b4bd404fb1eea64680
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Display flickering and occasional corruption were observed during panel
initialization on some TM_TL121BVMS07_00C panels when using an EMI-type
FPC.
According to Ilitek, this is caused by insufficient RX margin under
higher EMI conditions. Increasing receiver EQ, mask, bias, and voltage
settings improves signal tolerance and stabilizes display output.
Update the panel initialization code with the following parameters:
EQ:
P6_8F = 0xF0
Mask:
P8_82 = 0x13
P8_7D = 0x84
P8_7F = 0xDA
Bias:
P6_90 = 0x55
Voltage:
P5_3F = 0x47
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:479436242
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: Id8272103abfb94f4d4f4d915107eafb9d0f4edc9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
CFR default overrides use SM_OBJ_* kinds, but
write_numeric_option() compared them to CFR_TAG_OPTION_*,
so enum/number/bool overrides were always skipped.
Compare kinds against the expected SM_OBJ_* for each numeric
tag, then apply the override.
Change-Id: I02046974a7b0a3ef32973689833e1b0d38a5d6f4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90911
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A later patch changes the .config file which we use for our tests.
However that causes the PLATFORM_USES_FSP2_0 option to be enabled, which
in turn causes build errors in our tests, because the function is
obviously not defined in our tests. Create a stub function of sorts like
we do for other coreboot table entries.
It also moves the declaration of the `lb_string_platform_blob_version`
function to coreboot_tables.h, since it doesn't belong in the FSP header
file. Because of that we can also remove the
`if (CONFIG_PLATFORM_USES_FSP2_0)`
check, which makes the code a bit cleaner.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7721dfe4d287b2274a383bb7e5337b85a0f3f148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This patch adds Nova Lake specific device IDs to the header files and
driver-specific code.
Note: Device IDs D750h - D75Fh are intentionally omitted and will be
added in a future patch once validation is complete.
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: I00900c4f796b8bcc40f2bc09917172c71039c8a6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90748
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current implementation uses '%*s' which treats the calculated
str_len as a minimum field width. If the underlying string buffer is not
null-terminated, printk will continue reading past the buffer until it
encounters a null byte.
Switch to '%.*s' to correctly use the precision field, which specifies
the maximum number of characters to be printed from the string.
BUG=None
TEST=Able to dump FSP performance data with `DISPLAY_FSP_TIMESTAMPS`
Kconfig selected and meeting the FSP prerequisites. Verify that the
performance data table is printed correctly.
```
[INFO ] +---------------------------------------------------+
[INFO ] |------ FSP Performance Timestamp Table Dump -------|
[INFO ] +---------------------------------------------------+
[INFO ] | Perf-ID Timestamp(us) String/GUID |
[INFO ] +---------------------------------------------------+
[INFO ] 0 1242275 SEC/52c05b14-0b98-496c-bc3b04b50211d680
[INFO ] 50 1242282 PEI/52c05b14-0b98-496c-bc3b04b50211d680
[INFO ] 40 1242284 PreMem/52c05b14-0b98-496c-bc3b04b50211d680
```
Change-Id: Id95bd34b9c7d45d2c363339eb18adc5ac731c72b
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add DSI power-off commands for TM_TL121BVMS07_00C, so that payloads can
run it to properly disable the display.
Also refactor the init commands using MIPI_DCS_* macros to improve
readability.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I0e7da1d23c658d7f3594cbb651c229057810319c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90740
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD platforms the PSP can boot from different SPI CS lines
and do a recovery boot in case the default CS0 isn't usable.
Allow the SoC to provide the current boot_device CS line by
adding a new weak function.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9ed54b7979405d433f22458265f09701cda842e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add a hooks that will populate mem_info structure with DIMM data
obtained from OpenSIL. As the memory population may be SoC-specific,
call a SoC-specific hook to fill the data.
Change-Id: I0b489c685877ac56f45e0e3abd0bd1b64549585b
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The AMD fTPM uses the CRB interface, but doesn't implement all registers
defined in the TCG specification. Add a new driver that deals with the
reduced register set.
The reduced CRB MMIO register space has:
- A START register to ring the doorbell
- An error STATUS register with only one bit
- DMA address and size register for the CRB
- No other status or control registers
- No way to read current locality (assumption is locality 0)
- No interface ID register
- No read only registers
The TPM interface also assumes that the DRTM is always using locality 0.
The fTPM needs to access the SPI flash and this is currently done using
the PSP SMI handler. Thus the fTPM will only operate after SMM has been
set up.
The fTPM needs the PSP directory files type 0x04 and type 0x54. When
the regions are missing or corrupted the fTPM won't be operational.
Based off https://github.com/teslamotors/coreboot/tree/tesla-4.12-amd
TEST=Works on AMD glinda (Fam 1Ah).
This adds the following new log messages:
[DEBUG] PSP: Querying PSP capabilities...OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM: CRB buffer created at 0x7b5ee000
[SPEW ] fTPM: CRB TPM initialized successfully
[INFO ] Initialized TPM device fTPM
...
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM2 log created at 0x7b5b1000
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] ACPI: * TPM2
[DEBUG] ACPI: added table 4/32, length now 68
Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Move the MIPI panel init command parsing function
mipi_panel_parse_init_commands() and related macros and structs from
drivers/mipi/ to commonlib/mipi/, so that the function can be shared
with payloads.
In a follow-up patch, a 'poweroff' field will be added to the
panel_serializable_data struct and then passed to payloads, so that
payloads can utilize mipi_panel_parse_init_commands() to run the panel
poweroff commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I19011669f03d060e9f030b673687cbe5965d7e2f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The smmstore_lookup_region() function was using
fmap_locate_area_as_rdev_rw() directly, which only provides
direct SPI access. This bypassed the optimized lookup_store()
function that uses incoherent_rdev to enable memory-mapped
reads via the read-only device while keeping direct SPI writes
via the read-write device.
Change smmstore_lookup_region() to call lookup_store() instead,
enabling memory-mapped reads for the public API and matching
the behavior of the internal implementation.
This improves read performance for EFI options and other
consumers of the SMMSTORE region device. It also fixes an issue
where direct SPI reads were crossing 4k page boundaries on older
platforms (Broadwell and earlier) causing them to fail and the
fallback option to be used, leading to a disconnect between the
user-selected option and device beahvior.
TEST=build/boot google/guado, verify all CFR options work properly
and no errors in cbmem.
Change-Id: I34947be932ede19a3fe896fe0da6373035fe6db7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The MIPI camera driver currently validates SSDB parameters for all
devices using the driver. However, some devices (VCM/NVM) does not have
these parameters configured.
Wrap the SSDB verification logic in a check for
`INTEL_ACPI_CAMERA_SENSOR`. This prevents the driver from throwing
"Parameters not set" errors and failing to create ACPI devices for
non-sensor devices.
BUG=b:474223827
TEST=Build and boot fatcat, verify that MIPI initialization no longer
fails for non-sensor MIPI devices while still enforcing validation for
actual camera sensors.
Change-Id: I34ef416cdc9fa35fdca21e9fecaa8d7fc2914338
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90697
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Currently _Exx suppots the wake pin under 255, for Caboc it's wake pin
is 325 which is out of range.
This CL change to use _EVT method to enhance GPIO event handling.
BUG=b:463410386
TEST=Compiled and tested on google/redrix and google/caboc:
1. emerge-brya coreboot, emerge-brox coreboot
2. Check /proc/interrupts has ACPI:Event
2. Wait for WWAN device to enter suspended state
3. Insert SIM card and modem is able to wake up WWAN device
Change-Id: Ifbb83ab48bbe4876269010adb2710641bdc879a5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90492
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change Google's Rex touch device name from TH_SENSOR_GOOGLE to
TH_SENSOR_ELAN_REX to better reflect the specific vendor and platform
combination. This provides clearer identification and avoids generic
naming that could cause confusion with other Google touch
implementations.
BUG=none
TEST=This change cannot be tested in isolation as it only contains
naming changes. Testing requires hardware that supports Rex touchscreen
functionality, such as: Fatcat board with Google's specialized cable
connected to a Rex touchscreen. Verify that the new naming convention
works correctly with change:
https://review.coreboot.org/c/coreboot/+/89181 (This change uses the new
naming convention introduced here). Touch functionality should work
identically to before, with only the internal naming updated.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40bb33dee14e9a567ad9dfcf956f3a9cca26dcad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90645
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
This power resource is valid in S5, so correct the advertised level.
Change-Id: I208182a7633c03d818a5b8892d305e3bcd5b835f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Bluetooth only signal wake while in USB suspend (D2). It is not possible
for it to wake when in D3 (low-power mode) so D3 is incorrect.
Change-Id: I1c2052507dfae235140e667b9a5580b4a7a8cb5d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90609
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pic_width and pic_height fields of dsc_config are equivalent to
edid.mode.ha and edid.mode.va, respectively. To remove duplicate
information in panel_serializable_data, remove these two fields from
dsc_config.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: I7f1dd4b431a610fa928b29da420b0c0e0bef5fcc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90561
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.
Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.
Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DSM methods already have the full ASL generated by the acpigen
calls in a comment above the function, so there's no need for line-
by-line comments for the acpigen calls. Keep the comments for
acpigen_pop_len() as they do enhance readability.
TEST=n/a, non functional change
Change-Id: I95bbc0b36706a45883ea50b7947c6c0235f546f7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90544
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add validation checks in camera_enable() for required parameters:
- ssdb.lanes_used
- ssdb.platform
- rom_address (when rom_type is set)
- vcm_address (when vcm_type is set)
Remove default values for ssdb.platform and ssdb.lanes_used from
camera_fill_ssdb_defaults() since these parameters are now required
and validated. All boards in the tree explicitly set these values
in their devicetree configurations, so the defaults were never used.
Also remove the unused cio2 and cio2_config variables that were only
used for the lanes_used default logic.
Change-Id: Idcb84c25b94ed9259698aafba201cc4f4e0f1af7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90517
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add support for non-VGA devices (e.g., Intel IPU) in the generic
graphics driver by:
- Adding DOD_NONVGA bit definition per ACPI spec 6.5 table B-2
- Adding non_vga_device boolean field to device config structure
- Increasing device array size from 6 to 7 to accommodate IPU
- Updating ACPI _DOD generation to use DOD_NONVGA flag for non-VGA
devices instead of DOD_FW_DETECT
This allows proper ACPI enumeration of non-VGA devices whose power
is related to the VGA device, such as Intel Image Processing Units.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I60472e1232959fe407f63b4b8e6bffba995e7f79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90516
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Refactor the MIPI camera driver to support two ACPI device generation
modes via a Kconfig choice:
1. Windows/Linux mode (MIPI_ACPI_TYPE_WINDOWS_LINUX): Generates a
single ACPI device for the camera sensor and any associated VCM or
NVM devices on the same I2C bus. The IPU ACPI device is attached to
the iGPU, not standalone. This is the preferred method for Windows
and mainline Linux.
2. ChromeOS mode (MIPI_ACPI_TYPE_CHROMEOS): Generates separate ACPI
devices for each camera component (sensor, CIO2, VCM, NVM). The IPU
ACPI device is generated separately from the iGPU. This maintains
compatibility with the existing ChromeOS-style setup.
The implementation uses runtime conditionals to select between the two
modes. Common helper functions are shared between modes, while device-
specific logic is conditional based on the selected ACPI type.
The default selection is MIPI_ACPI_TYPE_CHROMEOS for ChromeOS builds and
MIPI_ACPI_TYPE_WINDOWS_LINUX otherwise.
Change-Id: I0bc4894aff04d6b296011e85d790d624890da055
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90522
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add support for Computer Vision Framework Support DSM UUID with ACPI-
compliant query handling and ASL documentation. Currently we are
always returning Zero (unsupported/disabled), but support will be
added in future patches.
This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I6db88285d757826fa0f3eb5aa4bb1cc4176b95b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90490
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add camera_generate_dsm_i2c_v2() to support the I2C V2 DSM UUID
(5815c5c8-c47d-477b-9a8d-76173176414b) which returns I2C device
addresses in a buffer format, rather than individually. Includes
ACPI-compliant function query handling (Arg2==0) and ASL code
documentation.
This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: Ifd35b53b21d0d1be9e9802059c724bf544ca1a1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90489
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename UUID macros to match external conventions used in Linux kernel
and Windows Camera DDK:
- SENSOR_NAME_UUID -> UUID_DSM_SENSOR
- SENSOR_TYPE_UUID -> UUID_DSM_I2C
Rename functions for clarity:
- camera_generate_dsm_sensor_name -> camera_generate_dsm_sensor
- camera_generate_dsm_sensor_type -> camera_generate_dsm_i2c
Add ACPI-compliant function query support (Arg2==0) to sensor DSM,
returning bitmask of supported functions as required by ACPI spec.
Add ASL documentation comment blocks above each DSM generator function
showing the generated ACPI code structure.
Improve variable naming (i2c_dev_count, i2c_dev_idx) for readability.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I38facaf85ea59aa82621d82555858c0d72b1ee30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Refactor camera_generate_dsm() to call separate functions for each
DSM UUID type, improving code organization and maintainability, in
preparation for adding the generation of additional DSM UUIDs in
subsequent patches.
This is a non-functional change.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I8b3fb6e3004ea30aa7c11217c9971bddb977ded5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90487
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.
TEST=build/boot google/drobit, verify UEFI DBX able to be successfully
updated via fwupd.
Change-Id: I8d6a2051f3ad50117d41cec2bbbe3aaafa7e65c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90287
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SSDT contains:
CreateByteField (PPOP, Local0, TPPF)
However, CreateByteField requires the source argument to be
(Buffer | String | Integer). PPOP is an OperationRegion, so
iasl correctly reports:
Error 6058 - Invalid type ([Region] found)
Per ACPI spec, OperationRegions must use CreateField rather than
CreateByteField. Replace the AML emission with:
CreateField (PPOP, Local0 * 8, 8, TPPF)
This reads one byte at an arbitrary offset inside the PPI
OpRegion and is fully standards-compliant. This isn't a
functional change, just "correct".
Test=boot starbook_mtl, verify iasl can decompile and recompile
SSDT and TPM is still operational.
Change-Id: If80bb5bf69562f8b904c1b315e95a0b5627efbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This update enhances the Intel touch driver by incorporating support for
newly added _DSD entries specific to I2C devices. The enhancements
include:
- Adding new entries in the I2C _DSD to enable configurations for
maximum frame size and interrupt delay settings.
- Introducing device-specific interrupt delay settings tailored for
Hynitron devices.
These changes ensure improved configurability and performance tuning for
supported devices. It is crucial to use this update with an operating
system that includes corresponding changes for this new support.
ATTENTION: This change requires a THC driver fix. If the OS does not
have the driver fix, please use LPSS I2C or disable the touchscreen
and touchpad. For instance, on the Google Fatcat board, use the
following CBI fw_config options:
TOUCHSCREEN field: TOUCHSCREEN_LPSS_I2C or TOUCHSCREEN_NONE
TOUCHPAD field: TOUCHPAD_LPSS_I2C or TOUCHPAD_NONE
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iaab8329c97247161395d203a5efa92c053acb3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89214
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The breaks for `if` and `else` are inconsistent; remove all breaks for
these.
Change-Id: Ie76f38387fd5ef330b432c0462cb1101571c73db
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The existing brightness level fallback logic duplicated the default
backlight value by hardcoding BRLV to 100% (0x64). This caused divergence
whenever a platform defined a different default brightness through BRIG[0].
This change removes the duplicated default and replaces it with a cached
brightness mechanism using BRVA (valid flag) and BRLV (cached level).
The firmware now:
- Caches the last brightness level exposed to the OS.
- Uses the cached level during early boot/resume when the OpRegion
(BCLM/BCLV) is not yet initialized.
- Falls back to BRIG[0] only when no cached brightness exists.
- Preserves the existing replay-detection logic to keep firmware and OS
brightness state aligned once the graphics driver is active.
This ensures consistent brightness reporting, avoids incorrect 0% fallback
values, and respects board-specific BRIG defaults.
No functional changes occur once the graphics driver has initialized the
OpRegion; the improvement only affects early boot/resume behavior and
eliminates duplicated platform policy.
Change-Id: I651dfd30aa0c283b4e0659e5d19051e1b58204fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since the structs are the same, we may as well use the ones directly
from the driver (since it implements the standard anyway).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I44116e5e977029c37e1bf9b9d8ce8d6c022b5b0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
