coreboot/src/soc/intel/common
Ravi Sarawadi ad10d4a977 soc/intel/cmn/blk/graphics: Reserve memory compression region
This commit reserves memory resources associated with the memory
bandwidth compression functionality for Intel Integrated Graphics
Devices (IGD). The reservation is achieved by identifying the memory
region in the Resource Hand-Off Blocks (HOB) through a specific GUID,
provided in the FSP integration guide, and then marking it as
reserved. This ensures that the memory compression functionality can
operate without interference from other processes.

BUG=b:441695812
TEST=On a Fatcat device with the MemoryBandwidthCompression UPD set to
     1, coreboot logs show both the detection of the HOB and the related
     memory resource marked as reserved.

     [DEBUG]  Memory Compression HOB found: base=0x100000000
              length=0x02400000
     [...]
     [DEBUG]  19. 0000000100000000-00000001023fffff: RESERVED

Change-Id: I21f247dd8aaa88d4ae4da70eb78f7decc1793777
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
2025-08-29 16:00:36 +00:00
..
acpi soc/intel/cmn/acpi: Refactor SPCO ASL method 2025-06-15 05:53:57 +00:00
basecode
block soc/intel/cmn/blk/graphics: Reserve memory compression region 2025-08-29 16:00:36 +00:00
pch
fsp_reset.c
hda_verb.c
hda_verb.h
Kconfig.common
Makefile.mk
mma.c
mma.h
nhlt.c
reset.c soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn 2025-02-25 17:37:13 +00:00
reset.h soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn 2025-02-25 17:37:13 +00:00
smbios.c
smbios.h
tco.h
tpm_tis.c
vbt.c
vbt.h