soc/intel/alderlake: Add 28W TDP support for RPL-P ID 8 (0xa716)
Add voltage regulator configuration for Intel Raptor Lake-P processor
with MCH ID 0xa716 (RPL_P_ID_8) at 28W TDP. This processor has a
4+4 core configuration.
- Add the MCH ID mapping to the 28W TDP processor variant
- Add VR configurations for loadline, ICC, TDC timewindow, and
TDC current limit tables
The VR configuration is adapted from the existing 28W variants.
TEST=Built and booted on hardware with MCH ID 0xa716. Verified
resolution of "Unknown MCH" errors and correct power limit
configuration. System boots successfully to OS.
Before:
[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 649 / 543 ms
[DEBUG] All HSPHY ports disabled, skipping HSPHY loading
[INFO ] Disabling PCH PCIE ClockGating+PowerGating.
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[INFO ] PCI 1.0, PIN A, using IRQ #16
...
[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 20 / 4 ms
[INFO ] Initializing devices...
[DEBUG] PCI: 00:00:00.0 init
[ERROR] unknown SA ID: 0xa716, skipped power limits configuration.
[DEBUG] PCI: 00:00:00.0 init finished in 7 msecs
After:
[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 542 / 537 ms
[DEBUG] All HSPHY ports disabled, skipping HSPHY loading
[INFO ] Disabling PCH PCIE ClockGating+PowerGating.
[INFO ] PCI 1.0, PIN A, using IRQ #16
...
[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 21 / 4 ms
[INFO ] Initializing devices...
[DEBUG] PCI: 00:00:00.0 init
[INFO ] CPU TDP = 28 Watts
[INFO ] CPU PL1 = 28 Watts
[INFO ] CPU PL2 = 28 Watts
[INFO ] CPU PL4 = 64 Watts
[DEBUG] PCI: 00:00:00.0 init finished in 14 msecs
Change-Id: I9d6f32f2f3fbf73e46a25d77e4dba7711ed70d5f
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
c15006eb0c