50099def6f
The current CBMEM top is situated at the base of 'dram_xbl_log' (0x81A00000), leaving only 4.4MB of usable memory below it. This space has become insufficient for the growing size requirements of the coreboot configuration tables and boot services. Relocate the CBMEM top to the base of the PIL region (0x866C0000). This move increases the available contiguous memory for CBMEM allocation from 4.4MB to 7.3MB, ensuring sufficient headroom for the tables and reducing fragmentation for the OS and runtime services. Changes: - Update cbmem_top_chipset() to return _dram_pil as the new boundary. - Update memlayout.ld documentation to reflect CBMEM's new position directly below the PIL region. TEST=Verified CBMEM initialization on Bluey; confirmed coreboot tables are correctly allocated at the new high-memory boundary and no overlaps occur with reserved regions. Change-Id: I26d95b952634ce06ed2171c75bc6a129c15ec3b8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90912 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Avi Uday <aviuday@google.com> |
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| x1p42100 | ||