coreboot/src
Matt DeVillier d1e1d36fff soc/intel: Use chipset.cb for UART device ops linking
Move UART device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from uart.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
UART controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: Id26dad7997d64bcaad53fa39be23e52cb47dcc1d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90916
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2026-01-28 13:38:19 +00:00
..
acpi acpi: Add enums for TPM2 start method 2026-01-14 17:03:18 +00:00
arch Makefile.mk: Remove "crt0" dead code 2026-01-25 19:05:42 +00:00
commonlib Revert "commonlib/list: Support circular list" 2026-01-27 17:41:30 +00:00
console console: Fix flushing for slow consoles 2025-10-02 22:44:46 +00:00
cpu Makefile.mk,cpu/intel/fit/Makefile.mk: introduce CBFS_REGIONS 2025-12-20 17:39:22 +00:00
device device/pciexp: Enable ASPM on root ports without endpoints 2026-01-28 13:31:02 +00:00
drivers drivers/option/cfr: Fix numeric default override 2026-01-28 13:37:52 +00:00
ec ec/lenovo/h8: Properly advertised used I/O 2026-01-25 19:23:22 +00:00
include tree: Remove Ice Lake PCI ID remnants 2026-01-28 13:36:23 +00:00
lib tests/lib/coreboot_table-test.c: Add lb_string_platform_blob_version 2026-01-23 21:38:33 +00:00
mainboard mb/purism/librem_jsl: Use device aliases in devicetree 2026-01-28 13:37:35 +00:00
northbridge device/dram/ddr3: Fill in voltage fields for SMBIOS type 17 2025-12-08 02:36:00 +00:00
sbom sbom: Fix build with merged bootblock and romstage 2025-07-07 14:29:29 +00:00
security drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs 2026-01-14 17:02:47 +00:00
soc soc/intel: Use chipset.cb for UART device ops linking 2026-01-28 13:38:19 +00:00
southbridge sb/intel/ibexpeak: Remove 6/7 series chipset PCI IDs 2026-01-16 16:46:49 +00:00
superio sio/nuvoton/common: Refactor nuvoton_pnp_*_config_state() 2026-01-03 03:40:12 +00:00
vendorcode vendorcode/amd/opensil: Add Turin OpenSIL 2026-01-28 13:32:33 +00:00
Kconfig arch/x86/ioapic.c: Support 8-bit IOAPIC IDs 2026-01-13 16:19:43 +00:00