6fd865f409
The AMD fTPM uses the CRB interface, but doesn't implement all registers defined in the TCG specification. Add a new driver that deals with the reduced register set. The reduced CRB MMIO register space has: - A START register to ring the doorbell - An error STATUS register with only one bit - DMA address and size register for the CRB - No other status or control registers - No way to read current locality (assumption is locality 0) - No interface ID register - No read only registers The TPM interface also assumes that the DRTM is always using locality 0. The fTPM needs to access the SPI flash and this is currently done using the PSP SMI handler. Thus the fTPM will only operate after SMM has been set up. The fTPM needs the PSP directory files type 0x04 and type 0x54. When the regions are missing or corrupted the fTPM won't be operational. Based off https://github.com/teslamotors/coreboot/tree/tesla-4.12-amd TEST=Works on AMD glinda (Fam 1Ah). This adds the following new log messages: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] TPM: CRB buffer created at 0x7b5ee000 [SPEW ] fTPM: CRB TPM initialized successfully [INFO ] Initialized TPM device fTPM ... [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] TPM2 log created at 0x7b5b1000 [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] ACPI: * TPM2 [DEBUG] ACPI: added table 4/32, length now 68 Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88247 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> |
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| intel | ||
| lockdown | ||
| memory | ||
| tpm | ||
| vboot | ||
| Kconfig | ||
| Makefile.mk | ||