Sean Rhodes 091ac10059 soc/intel/cnvi: Correct S-state level for CNVP ... This power resource is valid in S5, so correct the level that is set. This makes it match the reference code, and the CNVi Bluetooth power resource. Change-Id: I430cafafc0326dc189a337bf2b67cf200afc4f17 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90610 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-12-26 15:18:40 +00:00
..
alderlake	soc/intel/*: Add CFR option to enable/disable the Intel iGPU	2025-12-11 15:11:43 +00:00
apollolake	soc/intel/apollolake: Add CFR objects for existing options	2025-12-11 19:47:22 +00:00
baytrail	tree: Use boolean for s3resume	2025-10-23 13:34:15 +00:00
braswell	soc/intel/braswell/acpi: Add missing MMIO window below 4GB	2025-10-17 22:19:06 +00:00
broadwell	tree: Use boolean for s3resume	2025-10-23 13:34:15 +00:00
cannonlake	soc/intel/*: Add CFR option to enable/disable the Intel iGPU	2025-12-11 15:11:43 +00:00
common	soc/intel/cnvi: Correct S-state level for CNVP	2025-12-26 15:18:40 +00:00
denverton_ns	soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as appropriate	2025-08-02 01:46:21 +00:00
elkhartlake	soc/intel/*: Only skip PMC fallback on successful CSE reset	2025-12-11 00:11:06 +00:00
jasperlake	soc/intel/*: Add CFR option to enable/disable the Intel iGPU	2025-12-11 15:11:43 +00:00
meteorlake	soc/intel/*: Add CFR option to enable/disable the Intel iGPU	2025-12-11 15:11:43 +00:00
pantherlake	soc/intel/pantherlake: Add ChromeOS board-specific TDP setting	2025-12-23 14:16:08 +00:00
skylake	soc/intel/*: Add CFR option to enable/disable the Intel iGPU	2025-12-11 15:11:43 +00:00
snowridge	device/dram: Rename 'USE_DDRx' config options	2025-07-25 17:03:02 +00:00
tigerlake	soc/intel/*: Add CFR option to enable/disable the Intel iGPU	2025-12-11 15:11:43 +00:00
xeon_sp	soc/intel/*: Only skip PMC fallback on successful CSE reset	2025-12-11 00:11:06 +00:00
Makefile.mk