Maximilian Brune 97291b5838 soc/amd/cezanne: Optionally propagate UART0 through ACPI ... Unable to passthrough the UART0 in domU when UART1 enabled in dom0 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7ccf366dbac556f68096382644f3e72b13e2dbf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90210 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-11-27 17:55:20 +00:00
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cezanne	soc/amd/cezanne: Optionally propagate UART0 through ACPI	2025-11-27 17:55:20 +00:00
common	soc/amd/common/block/psp: Add comments	2025-09-25 16:06:54 +00:00
genoa_poc	soc/amd/genoa_poc/root_complex.c: Explain the order of IOHCs	2025-08-28 20:12:40 +00:00
glinda	soc/amd/common/block: Don't clobber SPI registers	2025-08-28 20:11:20 +00:00
mendocino	soc/amd/common/block: Don't clobber SPI registers	2025-08-28 20:11:20 +00:00
phoenix	soc/amd/common/block: Don't clobber SPI registers	2025-08-28 20:11:20 +00:00
picasso	soc/amd/common/block: Don't clobber SPI registers	2025-08-28 20:11:20 +00:00
stoneyridge	soc/amd/stoneyridge: Generate SATA ACPI registers at runtime	2025-11-14 16:28:19 +00:00
turin_poc	soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc	2025-10-24 21:38:41 +00:00