Kane Chen 713f809952 baytrail: there is a chance that USBPHY_COMPBG is set to 0 ... Due to some projects don't have the correct settings in devicetree.cb so put this change in case those projects without are setting in devicetree.cb BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly even there is no setting in devicetree Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://chromium-review.googlesource.com/209051 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>		2014-07-20 07:47:12 +00:00
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arch	armv8: correct dcache line size calculation	2014-07-18 22:44:11 +00:00
console	vboot2: implement select_firmware for pre-romstage verification	2014-06-30 18:45:09 +00:00
cpu	x86: Initialize drivers in SMM context if needed	2014-06-20 18:27:33 +00:00
device	i2c: Add software_i2c driver for I2C debugging and emulation	2014-05-19 20:34:31 +00:00
drivers	Support storm Spansion flash variety	2014-06-23 21:48:49 +00:00
ec	vboot2: read dev and recovery switch	2014-07-02 00:45:22 +00:00
include	cbmem console: expose empty functions	2014-07-12 01:09:10 +00:00
lib	vboot2: copy tlcl from vboot_reference as a preparation for vboot2 integration	2014-07-08 23:29:11 +00:00
mainboard	ryu: Add TPS65913 regs/init for VDD_CPU 1.0V	2014-07-20 07:46:57 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	baytrail: there is a chance that USBPHY_COMPBG is set to 0	2014-07-20 07:47:12 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	vboot2: copy tlcl from vboot_reference as a preparation for vboot2 integration	2014-07-08 23:29:11 +00:00
Kconfig	coreboot arm64: Add support for arm64 into coreboot framework	2014-05-15 23:52:58 +00:00