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baytrail: there is a chance that USBPHY_COMPBG is set to 0

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Due to some projects don't have the correct settings in devicetree.cb
so put this change in case those projects without are setting in devicetree.cb

BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
     checked the USBPHY_COMPBG is configured properly
     even there is no setting in devicetree

Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/209051
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This commit is contained in:
Kane Chen 2014-07-17 11:31:57 -07:00 • committed by chrome-internal-fetch
commit 713f809952
1 changed files with 3 additions and 1 deletions
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4
src/soc/intel/baytrail/ehci.c
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@ -94,10 +94,12 @@ static const struct reg_script ehci_hc_reset[] = {
static void usb2_phy_init(device_t dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?
0x4700 : config->usb2_comp_bg);
struct reg_script usb2_phy_script[] = {
/* USB3PHYInit() */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
config->usb2_comp_bg),
usb2_comp_bg),
/* Per port phy settings, set in devicetree.cb */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0,
config->usb2_per_port_lane0),