Duncan Laurie 5d166a0c4d broadwell: Changes from 2.2.0 ref code ... - The SATA CAP register setup was moved outside the refcode blob we run so it needs to be set up by coreboot again... - Slight tweak to fast ramp voltage for broadwell CPU BUG=chrome-os-partner:25491 BRANCH=None TEST=Build and boot on samus Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/214024 Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2014-08-25 20:53:09 +00:00
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arch	arm64: Make exceptions work	2014-08-22 05:47:40 +00:00
console	vboot2: implement select_firmware for pre-romstage verification	2014-06-30 18:45:09 +00:00
cpu	haswell: Update microcode revision	2014-07-29 04:37:18 +00:00
device	i2c: Add software_i2c driver for I2C debugging and emulation	2014-05-19 20:34:31 +00:00
drivers	spi: Support Macronix MX25U6435F SPI ROM.	2014-08-07 22:45:49 +00:00
ec	chromeec: provide proto v3 over i2c support	2014-08-07 22:38:07 +00:00
include	smbios: add funtion for smbios type17	2014-08-12 02:40:38 +00:00
lib	fix how to interpret board id read from gpios	2014-08-09 07:05:56 +00:00
mainboard	auron: Remove FUI code	2014-08-25 20:53:06 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	broadwell: Changes from 2.2.0 ref code	2014-08-25 20:53:09 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	vboot: Introduce kconfig variable for VBNV backing storage	2014-08-25 04:52:51 +00:00
Kconfig	Enable publishing of board ID where supported	2014-07-30 23:41:23 +00:00