We have known for a while that the old x86 model of calling init_timer()
in ramstage doesn't make sense on other archs (and is questionable in
general), and finally removed it with CL:219719. However, now timer
initialization is completely buried in the platform code, and it's hard
to ensure it is done in time to set up timestamps. For three out of four
non-x86 SoC vendors we have brought up for now, the timers need some
kind of SoC-specific initialization.
This patch reintroduces init_timer() as a weak function that can be
overridden by platform code. The call in ramstage is restricted to x86
(and should probably eventually be removed from there as well), and
other archs should call them at the earliest reasonable point in their
bootblock. (Only changing arm for now since arm64 and mips bootblocks
are still in very early state and should sync up to features in arm once
their requirements are better understood.) This allows us to move
timestamp_early_init() into arch code, so that we can rely on timestamps
being available at a well-defined point and initialize our base value as
early as possible. (Platforms who know that their timers start at zero
can still safely call timestamp_early_init(0) again from platform code.)
BRANCH=None
BUG=None
TEST=Booted Pinky, Blaze and Storm, compiled Daisy and Pit.
Change-Id: Iece1614b7442d4fa9ca981010e1c8497bdea308d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234062
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This configures I2S1 and the codec MCLK muxes to pass the PCM
audio data to the RT5677 codec. Once depthcharge RT5677 codec
driver changes are in, audio 'beeps' should be heard on boot
(Ctrl-U / devmode/recmode).
BUG=chrome-os-partner:32582
BRANCH=none
TEST=Built and booted Ryu/A44.
Change-Id: Ib071bcb41fba8f6d628a386ed233ec84a54b0323
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/233945
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With this change, audio 'beeps' are heard on boot if Ctrl-U is
pressed, or devmode/recmode is entered. I also tested via an
explicit call to VbExBeep in the kernel boot path. Note that
a couple of Rush CLs for depthcharge are needed for audio, too.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=as above. Built and booted Rush/Norrin64.
Change-Id: Ia37f077569afd806ce6574c4c58813fd7aca1644
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/233671
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
add the samsung-4GB and hynix-4GB lpddr inf file,
and use ram_id 1000 correspond to samsung-4GB lpddr
use ram_id 1001 correspond to hynix-4GB lpddr
BUG=chrome-os-partner:33269
TEST=Boot veyron_speedy normal
BRANCH=None
Change-Id: I55b6968c642df8c1f579e518232ab5d278e7e12f
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/233859
Reviewed-by: Julius Werner <jwerner@chromium.org>
Essentially a copy of veyron_jerry for now
BUG=chrome-os-partner:33269
TEST=emerge-veyron_speedy coreboot
BRANCH=None
Change-Id: Ife457db4fd67fe69bcd4082694b3372eccfb304b
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/233822
Reviewed-by: Julius Werner <jwerner@chromium.org>
The only way to reliably reset an SD card in an unknown state is by
power-cycling. Since a kernel may crash and reboot at any point, SD
cards may be left in one of them fancy high-throughput modes that
depthcharge (or, in fact, a newly booting kernel without prior
knowledge) doesn't support, so we need to reset the card on every boot.
This patch adds support to turn off an RK808 regulator completely and
uses that to turn off SD card power rails in early romstage. The time
until configure_sdmmc() in ramstage turns them back on should be more
than enough to drain the power rail for an effective power-cycle.
BRANCH=None
BUG=chrome-os-partner:34289
TEST=Booted a Pinky from SD card, noticed that it works before and
after this patch.
Change-Id: I904b2d23ca35f765c000f9bee7637044f674eff9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233713
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Due to CL https://chromium-review.googlesource.com/231250,
depthcharge now detects gpio state based on gpio configurations
done by coreboot instead of redoing configuration at
depthcharge. However, PWR button and LID open pins have not
been configured in coreboot. So, add the missing code here.
Otherwise, TOT coreboot/depthcharge rush build can not load
in kernel.
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build rush and test with pwr button press and lid switch
Change-Id: I6c322cd987967920f236aae653294db079678408
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/233322
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit 257aaee9e3 (arm: Add bootblock_mainboard_early_init() for
pre-console initialization) inadvertently moved the timer initialization
after console initialization for IPQ806x, which is apparently not a good
idea for this platform. This patch solves the issue by moving
init_timer() to bootblock_mainboard_early_init(), which is the new hook
explicitly provided to perform pre-console tasks.
BRANCH=None
BUG=None
TEST=Built and booted Storm with 257aaee9e reverted. Noticed that it was
already broken. Bisected coreboot and tracked down breakage to commit
a126a62f (ipq8064: use the new utility to build bootblock). Built and
booted successfully with this patch and a revert of a126a62f to confirm
that the bug in question here is fixed.
Change-Id: Ie4aa2d06cb6fda6d5ff8dd5ea052257fb7b8a24b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There are several use cases for performing a certain task when CBMEM is
first set up (usually to migrate some data into it that was previously
kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them
differently: timestamp migration is called explicitly from
cbmem_initialize(), certain x86-chipset-specific tasks use the
CAR_MIGRATION() macro to register a hook, and the CBMEM console is
migrated through a direct call from romstage (on non-x86 and SandyBridge
boards).
This patch decouples the CAR_MIGRATION() hook mechanism from
cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer
description of what it really does. All of the above use cases are
ported to this new, consistent model, allowing us to have one less line
of boilerplate in non-CAR romstages.
BRANCH=None
BUG=None
TEST=Built and booted on Nyan_Blaze and Falco with and without
CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after
boot (and the resume log after S3 resume on Falco). Compiled for Parrot,
Stout and Lumpy.
Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Non-x86 boards currently need to hardcode the position of their CBFS
master header in a Kconfig. This is very brittle because it is usually
put in between the bootblock and the first CBFS entry, without any
checks to guarantee that it won't overlap either of those. It is not fun
to debug random failures that move and disappear with tiny alignment
changes because someone decided to write "ORBC1112" over some part of
your data section (in a way that is not visible in the symbolized .elf
binaries, only in the final image). This patch seeks to prevent those
issues and reduce the need for manual configuration by making the image
layout a completely automated part of cbfstool.
Since automated placement of the CBFS header means we can no longer
hardcode its position into coreboot, this patch takes the existing x86
solution of placing a pointer to the header at the very end of the
CBFS-managed section of the ROM and generalizes it to all architectures.
This is now even possible with the read-only/read-write split in
ChromeOS, since coreboot knows how large that section is from the
CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be
changed on systems that place other data next to coreboot/CBFS in ROM).
Also adds a feature to cbfstool that makes the -B (bootblock file name)
argument on image creation optional, since we have recently found valid
use cases for CBFS images that are not the first boot medium of the
device (instead opened by an earlier bootloader that can already
interpret CBFS) and therefore don't really need a bootblock.
BRANCH=None
BUG=None
TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco.
Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229975
Some projects (like ChromeOS) put more content than described by CBFS
onto their image. For top-aligned images (read: x86), this has
traditionally been achieved with a CBFS_SIZE Kconfig (which denotes the
area actually managed by CBFS, as opposed to ROM_SIZE) that is used to
calculate the CBFS entry start offset. On bottom-aligned boards, many
define a fake (smaller) ROM_SIZE for only the CBFS part, which is not
consistently done and can be an issue because ROM_SIZE is expected to be
a power of two.
This patch changes all non-x86 boards to describe their actual
(physical) ROM size via one of the BOARD_ROMSIZE_KB_xxx options as a
mainboard Kconfig select (which is the correct place to declare
unchangeable physical properties of the board). It also changes the
cbfstool create invocation to use CBFS_SIZE as the -s parameter for
those architectures, which defaults to ROM_SIZE but gets overridden for
special use cases like ChromeOS. This has the advantage that cbfstool
has a consistent idea of where the area it is responsible for ends,
which offers better bounds-checking and is needed for a subsequent fix.
Also change the FMAP offset to default to right behind the (now
consistently known) CBFS region for non-x86 boards, which has emerged as
a de-facto standard on those architectures and allows us to reduce the
amount of custom configuration. In the future, the nightmare that is
ChromeOS's image build system could be redesigned to enforce this
automatically, and also confirm that it doesn't overwrite any space used
by CBFS (which is now consistently defined as the file size of
coreboot.rom on non-x86).
CQ-DEPEND=CL:231576,CL:231475
BRANCH=None
BUG=chromium:422501
TEST=Built and booted on Veyron_Pinky.
Change-Id: I4fce5a56a8d72f4c4dd3a08c129025f1565351cc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229974
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With this descriptor added ramstage properly allocates memory
resources and creates entries in coreboot table. This also allows to
proceed to booting depthcharge, as it now can be loaded into the
existing memory.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the set of patches applied the firmware properly finds
depthcharge in CBFS, uncompresses it and attempts to start:
...
Booting payload fallback/payload from cbfs
Loading segment from rom address 0x9b000058
code (compression=1)
New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe
Loading segment from rom address 0x9b000074
Entry Point 0x80124038
Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
lb: [0x0000000080000000, 0x0000000080013858)
Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
using LZMA
[ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090
Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054
dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129
Jumping to boot code at 80124038
ERROR: dropped a timestamp entry
CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes
entry = 80124038
Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232571
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses the new bootblock_mainboard_early_init() hook to run the
UART pinmuxing on rk3288-based boards before initializing the console.
This allows us to get rid of the hacky second console_init() call in
bootblock_soc_init(). We can also simplify the pinmux selection a bit
since we know that a given board always uses the same UART (still keep
an assert around to be sure, though).
BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky.
Change-Id: Ia56c0599a15f966d087ca39181bfe23abd262e72
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231942
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On most platforms, enabling the console and exception handlers are
amongst the very first things you want to do, as they help you see
what's going on and debug errors in other early init code. However, most
ARM boards require some small amount of board-specific initialization
(pinmuxing, maybe clocks) to get the UART running, which is why
bootblock_mainboard_init() (and with it almost all of the actual
bootblock code) always had to run before console initialization for now.
This patch introduces an explicit bootblock_mainboard_early_init() hook
for only that part of initialization that absolutely needs to run before
console output. The other two hooks for SoC and mainboard are moved
below console_init(). This model has already proven its worth before in
the tegra124 and tegra132 custom bootblocks.
BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky. Compiled for Daisy, Storm and Ryu.
Change-Id: I4257b5a8807595140e8c973ca04e68ea8630bf9a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231941
This patch makes some slight changes to the way bootblock_cpu_init() and
bootblock_mainboard_init() are used on ARM. Experience has shown that
nearly every board needs either one or both of these hooks, so having
explicit Kconfigs for them has become unwieldy. Instead, this patch
implements them as a weak symbol that can be overridden by mainboard/SoC
code, as the more recent arm64_soc_init() is also doing.
Since the whole concept of a single "CPU" on ARM systems has kinda died
out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had
already been done on Storm/ipq806x, which is now adjusted to directly
use the generic hook.) Also add a proper license header to
bootblock_common.h that was somehow missing.
Leaving non-ARM32 architectures out for now, since they are still using
the really old and weird x86 model of directly including a file. These
architectures should also eventually be aligned with the cleaner ARM32
model as they mature.
BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky. Compiled for Storm and confirmed in the
disassembly that bootblock_soc_init() is still compiled in and called
right before the (now no-op) bootblock_mainboard_init().
Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231940
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This CL makes slight changes to the ChromeOS-specific GPIO definitions
of Tegra and Rockchip boards to prepare them for new features in
depthcharge. It adds descriptions for the EC in RW and reset GPIOs,
changes the value Tegra writes into the (previously unused) 'port' field
to describe the complete GPIO information, and removes code to sample
some GPIOs that don't need to be sampled at coreboot time (to help
depthcharge detect errors and avoid using a stale value for something
that should always represent the current state).
BRANCH=None
BUG=None
TEST=None (tested together with depthcharge patches)
Change-Id: I36bb16c8d931f862bf12a5b862b10cf18d738ddd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231222
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since CL:226662, all TPMP accessing should be removed as well,
else it will cause fox_wtm2 coreboot failed on build.
BUG=none
BRANCH=none
TEST=./setup_board --board=fox_wtm2 && emerge-fox_wtm2 coreboot
CQ-DEPEND=CL:226662
Change-Id: Ia0eebb1924bbb23979c880f7d05600a0cf1e4ca3
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/232165
Reviewed-by: Wei Shun Chang <wei.shun.chang@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Update non-vboot2 memlayout:
1) Add timestamp region
2) Increase ramstage size
3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot
upstream board can also use this layout.
BUG=None
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of
vboot2.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f
Reviewed-on: https://chromium-review.googlesource.com/231547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
A couple of regs need to be poked to allow audio output
from this part on Ryu P0/P1. It will be replaced by two
non-configurable amps on P3.
BUG=none
BRANCH=none
TEST=Build/flashed on Ryu P1, dumped AD4567 (I2C6 dev 0x34)
regs and confirmed settings.
Change-Id: I8999843646927dbd07a179ede973ba5f1eb97167
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/231384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds Cypress gen5 trackpad device supported in auron
platform.
The new Cypress gen5 trackpad's I2C address is 0x24 which is different
from the old trackpad device's I2C address 0x67.
BRANCH=None
BUG=None
TEST=None
Signed-off-by: Dudley Du <dudley.dulixin@gmail.com>
Change-Id: I4a80d6a5b63b4ec3a0d38258886b1979a12377ea
Reviewed-on: https://chromium-review.googlesource.com/230254
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Dudley Du <dudl@cypress.com>
Tested-by: Dudley Du <dudl@cypress.com>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Port over a few recent changes that were uploaded before the Mighty
board landed.
BRANCH=None
BUG=None
TEST=Booted on a Pinky rev2, went as far as you'd expect.
Change-Id: I546dbc41ccd191159e96b851424fcb37902a57ec
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231691
Limit power to 12W at 90C and remove limit at 85C.
BUG=chrome-os-partner:33995
BRANCH=none
TEST=manual:
To have the CPU consume maximum power it is necessary to stress
both the CPU and the GPU. Bastion (chrome.supergiantgames.com)
and/or webglsamples.googlecode.com can be useful for this.
Testing this properly requires a script to report the running
average power readings. The watch_power.sh script is attached
to this issue in the partner tracker.
1) Run watch_power.sh continuously:
localhost ~ # watch -n 0 bash -e /tmp/watch_power_v2.sh
2) Start WebGL Aquarium (or other stress apps). The power draw should
be close to 15W if under enough load.
3) Watch until temperature climbs above 90C and is caught by
the thermal zone 10 second poll, this can be sped up by blocking
or removing the fan.
4) The ACPI thermal zone states should change to reflect that
active[2] is now enabled and power consumption should drop to 12W.
5) Stop the stress apps and wait until the CPU cools off again,
enable the fan again if it was removed.
6) The ACPI thermal zone state should switch back to active[3].
Signed-off-by: Wei Shun Chang <wei.shun.chang@intel.com>
Change-Id: If6be36f7b8eed9347ed60b90e5a265f4f8d31548
Reviewed-on: https://chromium-review.googlesource.com/231382
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Based on TPS65913, the max LDO turn on time is 500us. Since it is requested
the default delay of 500us when calling function pmic_write_reg(), it is
safe to remove this 100ms delay.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I53aecc273484edfa502231b44f6bcd7f5d8f9331
Reviewed-on: https://chromium-review.googlesource.com/231170
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Implement VOP and eDP drivers, vop and edp clock configuration,
framebuffer allocation and display configuration logic.
The eDP driver reads panel EDID to determine panel dimensions
and the pixel clock used by the VOP.
The pixel clock is generating using the NPLL.
BUG=chrome-os-partner:31897
TEST=Booted Veyron Pinky and display normal
BRANCH=None
Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/219050
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add a new memory type for the next build, and rename the existing
ones to drop the Gb suffix.
BUG=chrome-os-partner:33924
BRANCH=samus
TEST=build and boot on samus
Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230769
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently the rt5677 codec outputs 6MHz PDM clock which is
out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS
pin is pulled down to PGND with a 47k resistor, so the
expected PDM clock is 64*FS (~3MHz) according to its datasheet.
The corresponding kernel patch that adds the PDM clock config
option is https://chromium-review.googlesource.com/#/c/230303/
BUG=chrome-os-partner:33303
BRANCH=samus
TEST=flash coreboot with this patch and see PDM CLK went
from 6MHz to 3MHz on samus with a scope.
Change-Id: I09acdf47bab4f641981491a84197de234918435e
Signed-off-by: Ben Zhang <benzh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230344
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz)
for MCLK1, I2S1 for input. AHUB needs all of its child
peripherals taken out of reset and enabled, too.
This just sets up the audio clocks. More work still to
be done in the codec driver, and some kind of stub needs
to be created/hacked to set up the AD4567 speaker amp
regs for mono output on P1.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=Dumped clock regs and saw correct values
Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229993
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This value apparently changed to 0x27 in the hardware but was
never adjusted in firmware.
BUG=chrome-os-partner:33790
BRANCH=samus
TEST=build and boot on samus
Change-Id: I10ca7b77068491e143f8bf2463b481eada910618
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy.
BUG=none
BRANCH=ToT
TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan,
blaze, parrot, rambi, samus, storm, pinky with default configuration.
panther and stumpy are not tested because they currently don't build on ToT.
Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/227940
Reviewed-on: https://chromium-review.googlesource.com/229602
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When displaying a 800x600 bitmap on 2560x1800 panel, the image
is shown very small. So, set the fb to 1280x800 (based on tegra
dsi driver default mode setting), a 800x600 image can be shown
relatively proportional to panel size.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa
Reviewed-on: https://chromium-review.googlesource.com/229912
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
panel spec such as resoultion, bits per pixel are
needed to pass to depthcharge/payload for displaying
bitmap onto panel.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/227203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This should allow the max98090 codec to play beeps via
AHUB/I2S1 thru the depthcharge sound driver.
BUG=none
BRANCH=none
TEST=Saw max98090 codec init signon and register dump.
No sound yet.
Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229496
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Mike Frysinger <vapier@chromium.org>
Like most newer Chromebooks, Pinky and Jerry do not have physical
dev switches.
BUG=chrome-os-partner:33395
BRANCH=none
TEST=built and booted on Pinky, crossystem prints a valid value for
devsw_cur instead of an error.
Change-Id: I186518a59699d293c7938221b3ae45b27361c255
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229680
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the
power button GPIO changed polarity to low, the 5V_DRV pin for USB power
was moved to the AP again (welcome back!), and the EMMC_RST_L is now
finally on a port with the right IO voltage so we don't need any weird
pull-up tricks anymore. Since there are very few Jerry rev1s around,
we'll just move it over to the new code directly without introducing
board ID differences (also, because I have no idea how they stuffed it
this time... is this one actually called rev2?).
BRANCH=None
BUG=None
TEST=Still boots on my Pinky rev2, though that doesn't say much.
Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229010
Reviewed-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This patch ports commit 567f616f (rk3288: slowly raise to max cpu
voltage to prevent overshoot) to Veyron_Jerry. It also fixes include
ordering and some comment grammar in the affected code.
BRANCH=None
BUG=chrome-os-partner:32716
TEST=None
Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
It can't compile due to tpmp flag was removed in nvs.h
BRANCH=none
BUG=none
TEST=compile ok and boot to OS on pearlvalley
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I718b70c6194365ee19b93224b52b7bcf3a5055d0
Reviewed-on: https://chromium-review.googlesource.com/228975
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Tested-by: Kane Chen <kane.chen@intel.com>
1. Add page address, an i2c address, into register address table
2. Add pmic read function
3. Add more registers and setting values.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I227b3e9390e6fc020707d4730c19945760df6ca2
Reviewed-on: https://chromium-review.googlesource.com/226902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the
generic gpio_get_binaries() function to read RAM_ID GPIOs.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=built and booted on pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115
Reviewed-on: https://chromium-review.googlesource.com/227249
Reviewed-by: Julius Werner <jwerner@chromium.org>
Take codec out of reset (GPIO_PH1 aka CODEC_RST_L) and enable LDO2
(GPIO_PR2/KB_ROW2 aka AUDIO_ENABLE). Muxes are setup and the two
GPIOs are set to output and driven high.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=RealTek ALC5677 codec shows up in I2C6 scan at address 0x2D,
can read/write registers.
Change-Id: Iedce7bb9f8e61d3b8cd693fc5e567323d89f8046
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/228920
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Proto 0,1,2 boards had pwr btn active high. Proto 3 onwards boards will have pwr
btn active low. Thus, select power btn polarity based on board id.
BUG=chrome-os-partner:33545
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu proto 1.
Change-Id: Icdf51b9324385de00f5787e81018518c5397215f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/229011
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This will be connected to the coded for firmware upload.
BUG=chrome-os-partner:33495
BRANCH=samus
TEST=build and boot on samus, check that GSPI driver is loaded
Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228835
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This combines the board version reading and parsing to
a separate file that is compiled in both romstage (for
early serial output) and ramstage (for smbios tables).
It also adds a new board version that is wrapped back
to number zero as we are running out of available IDs.
BUG=chrome-os-partner:32895
BRANCH=samus
TEST=build and boot on samus EVT1 and EVT2 and check
for proper board versions reported in console and smbios.
Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229041
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
