ryu: Add speaker amp config for AD4567 on P0/P1
A couple of regs need to be poked to allow audio output from this part on Ryu P0/P1. It will be replaced by two non-configurable amps on P3. BUG=none BRANCH=none TEST=Build/flashed on Ryu P1, dumped AD4567 (I2C6 dev 0x34) regs and confirmed settings. Change-Id: I8999843646927dbd07a179ede973ba5f1eb97167 Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/231384 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -22,6 +22,7 @@
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#include <boot/coreboot_tables.h>
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#include <cbmem.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <elog.h>
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#include <memrange.h>
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#include <soc/addressmap.h>
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@ -204,6 +205,37 @@ static void setup_audio(void)
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clock_enable_audio();
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}
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#define AD4567_DEV 0x34
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#define PWR_CTL 0
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#define DAC_CTL 2
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#define SPWDN (1 << 0)
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#define DAC_MUTE (1 << 6)
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#define DAC_FS (0x7 << 0)
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#define SR_32K_48KHZ 0x2
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static void enable_ad4567_spkr_amp(void)
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{
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uint8_t reg_byte;
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if (board_id() >= BOARD_ID_PROTO_3)
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return;
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/*
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* I2C6, device 0x34 is an AD4567 speaker amp on P0/P1.
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* It needs to have a couple of regs tweaked to turn it on
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* so it can provide audio output to the mono speaker on P0/P1.
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*/
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i2c_readb(I2C6_BUS, AD4567_DEV, PWR_CTL, ®_byte);
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reg_byte &= ~SPWDN; // power up amp
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i2c_writeb(I2C6_BUS, AD4567_DEV, PWR_CTL, reg_byte);
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/* The next 2 settings are defaults, but set them anyway */
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i2c_readb(I2C6_BUS, AD4567_DEV, DAC_CTL, ®_byte);
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reg_byte &= ~DAC_MUTE; // unmute DAC (default)
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reg_byte &= ~DAC_FS; // mask sample rate bits
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reg_byte |= SR_32K_48KHZ; // set 32K-48KHz sample rate (default)
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i2c_writeb(I2C6_BUS, AD4567_DEV, DAC_CTL, reg_byte);
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}
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static void mainboard_init(device_t dev)
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{
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soc_configure_funits(funits, ARRAY_SIZE(funits));
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@ -213,6 +245,8 @@ static void mainboard_init(device_t dev)
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i2c_init(I2C6_BUS);
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setup_audio();
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/* Temp hack for P1 board: Enable speaker amp (powerup, etc.) */
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enable_ad4567_spkr_amp();
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elog_init();
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elog_add_boot_reason();
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