mainboard/$VENDOR/$BOARD/initram.c. It's pointless to have it in the
southbridge code as well.
Kill it in the southbridge code and use mainboard code only.
Thanks to Segher for rediscovering this bug.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@830 f3766cd6-281f-0410-b1cd-43a5c92072e9
person can fix it.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@820 f3766cd6-281f-0410-b1cd-43a5c92072e9
next step is to fix up this:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
make: exit 2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
image, and fails:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
code to use it. That makes the code more readable and also less
error-prone.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@805 f3766cd6-281f-0410-b1cd-43a5c92072e9
udelay() instead which does the same, and achieve better abstraction.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@799 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is the part of the acked patch which was to become r649 but missed
in the check in.
I'm reusing the signoff and ack.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@796 f3766cd6-281f-0410-b1cd-43a5c92072e9
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.
This pepares the way for additional optimizations during compile and
link time.
Build tested and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
issues in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@776 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@774 f3766cd6-281f-0410-b1cd-43a5c92072e9
But we can start to build it now.
Add the serengeti. Now comes the fun part: trying to get it to build.
Be aware that things have changed.
Stage1 is going to need to start up the APs, load the microcode, before we can event attempt to run initram.
So we're going to need more sophisticated code than we've had in the past.
Note also that copying cache_as_ram_auto.c and hacking it is NOT an option. We're going to have to
recreate stage 1 and initram from scratch. I expect this to improve the code anyway.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com
git-svn-id: svn://coreboot.org/repository/coreboot-v3@773 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add the 8152.
Add a config variable ACPI_TABLE
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@772 f3766cd6-281f-0410-b1cd-43a5c92072e9
I would really like to remove ops_pci from the device struct.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@771 f3766cd6-281f-0410-b1cd-43a5c92072e9
Rename files and functions as needed.
There is regularity to the naming. Stage1 stuff is called stage1_*. The rest is not.
Most .c files have a corresponding .dts. The code is simpler and smaller and has less
duplication.
Most (all) romcc artifacts removed.
I've made a lot of effort to get copyright headers done correctly, using 'svn log'.
next are the 8132, 8151, and serengeti, then comes simnow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@767 f3766cd6-281f-0410-b1cd-43a5c92072e9
northbridge.c is marked for deletion, so don't sit up waiting for it to come home.
pci functions are in pci.c
domain functions are in domain.c
cpu functions are in cpu.c; cpu.c may move in the future to, say, someplace like cpu/amd/k8.
common functions are in common.c
These are still not set up quite right. I used svn copy to create the new files.
Geode builds fine. Anybody want to guess why this happens on k8? It's not clear to me.
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c: At top level:
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:60: error: ‘pci_conf1_read_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:33: error: previous definition of ‘pci_conf1_read_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:66: error: ‘pci_conf1_read_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:34: error: previous definition of ‘pci_conf1_read_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:72: error: ‘pci_conf1_read_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:35: error: previous definition of ‘pci_conf1_read_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:78: error: ‘pci_conf1_write_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:36: error: previous definition of ‘pci_conf1_write_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:84: error: ‘pci_conf1_write_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:37: error: previous definition of ‘pci_conf1_write_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:90: error: ‘pci_conf1_write_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:38: error: previous definition of ‘pci_conf1_write_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:116: error: ‘pci_conf1_find_on_bus’ redeclared as different kind of symbol
include/device/pci_ops.h:39: error: previous definition of ‘pci_conf1_find_on_bus’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:151: error: ‘pci_conf1_find_device’ redeclared as different kind of symbol
include/device/pci_ops.h:40: error: previous definition of ‘pci_conf1_find_device’ was here
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@764 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remove stage1.h -- not needed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@763 f3766cd6-281f-0410-b1cd-43a5c92072e9
This fixes a genuine bug in the MCP55 code.
Moving this away from PCI ops is the next goal.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@762 f3766cd6-281f-0410-b1cd-43a5c92072e9
the system a bit so I am going to let this one get acked and I won't
push
any more patches until this goes through.
Add lpc support.
Make things compile lpc.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
And also:
That code is really buggy. I wonder how/if it ever worked in v2. If you
address the comments below, this is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Comments (mostly) addressed. That said, I don't change functional code
that I know works -- we can fix that later. The ops_pci is addressed by
Carl-Daniel's patch.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@756 f3766cd6-281f-0410-b1cd-43a5c92072e9
We will revisit it later.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@748 f3766cd6-281f-0410-b1cd-43a5c92072e9
These both compile. There is an unresolved issue w.r.t. the DEBUG
check in usb2. How do we want this in v3?
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@747 f3766cd6-281f-0410-b1cd-43a5c92072e9
This includes using consistent (C) lines, adding email addresses,
and so on. The file southbridge/nvidia/mcp55/dts was never edited
by Yinghai Lu (thus removing his (C) line) and would be too trivial
anyway...
The changes (though trivial) were also informally acked by Ron on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@744 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add pci device. This compiles with no errors, no warnings.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
With the comments addressed:
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
I left the #if 1 in. It was there for a reason, we just don't know what it was.
I am reluctant to move such 'markers' at present.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@741 f3766cd6-281f-0410-b1cd-43a5c92072e9
Modify all functions to use the new v3 pci operations calling conventions.
use udelay for delays.
Add the USB debug support function.
This is compiling pretty well for me save for the missing hypertransport function.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@731 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@724 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is not nearly complete, but just the current state of my tree.
k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.
The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.
Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@713 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@701 f3766cd6-281f-0410-b1cd-43a5c92072e9
patch uses byte pointer and the MMIO read and write functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@696 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Eliminate a few redundant dev_find_pci_device() calls.
- Fix a compile warning intruduced in r689.
This should be an equivalence transformation.
Build tested on norwich, db800, alix.1c, alix.2c3, dbe62, dbe61.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@692 f3766cd6-281f-0410-b1cd-43a5c92072e9
Most importantly it fixes a simple programming error which made it so most of
the sets on the USB were not doing anything. The bug is also in V2.
With this fix, the DBE62 USB ports all work!
If someone clones the fix to V2, it will also fix V2. Or, we can just convince
you to move forward to V3 :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@689 f3766cd6-281f-0410-b1cd-43a5c92072e9
USB EHCI power control registers to power enables pins 1 and 2.
Why doesn't port 4 work? Who knows. That's a problem for another day.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@688 f3766cd6-281f-0410-b1cd-43a5c92072e9
Set manual settings for dbe62 PLL; the auto settings are giving
slightly wrong values
Add call to dumplxmsr in dbe62 initram main()
Change dumplxmsr to void parameter
Add dumplxmsrs function to geodelx raminit support code
Correct spelling of CAS.
The big one: set spd variables correctly.
The not so big one: there is a bug in com2 enable I don't understand.
For now comment out two offending lines. The cs5536 debug prints
should be reduced later.
Change fuctory to factory. It's funny but confusing.
This patch also takes into account carl-daniel and uwe's comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@649 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on dbe62. I had to run cs5536/stage1.c through indent -kr -i8 because emacs is somehow
confused by parts of it. Weird. indent made some parts ugly, at least to my eyes. Oh well.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@638 f3766cd6-281f-0410-b1cd-43a5c92072e9
This includes:
- the working power button patch.
- onchipuart2 for very early startup -- this will be replaced with a better mechanism soon.
- dts mod for powerbutton on cs5536
- dbe62 dts fix for COM1 setup
- ram check call in dbe62 initram.c
- Carl-Daniel's fix to detect incorrect access to spd variables.
- more debug prints in geodelx northbridge support code.
This is cumulative since we're lagging on acks a bit and it's hard to keep this
stuff all seperated out since it involves a common set of files. I'd like to get
it acked and in tree today if possible. It's a very small set of lines changed so please
forgive me for the cumulative nature.
Thanks
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@636 f3766cd6-281f-0410-b1cd-43a5c92072e9
Factor out write_pirq_routing_table() for all GeodeLX targets.
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
tested on alix1c. Boots, USB, graphics, and ethernet all work.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@629 f3766cd6-281f-0410-b1cd-43a5c92072e9
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.
svn is unable to create a valid patch for what I did, so I'll have to
commit this myself. To reproduce, perform the following commands, then
apply the patch:
svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h
svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h
svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h
svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
tested on alix1c. Boots, USB, graphics, and ethernet all work.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@628 f3766cd6-281f-0410-b1cd-43a5c92072e9
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which
will come once this is in.
This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did
not work out, and it revealed a flaw in the design. The result?
- no more ids in the various dts files.
- the constructor struct is gone -- one less struct, nobody liked the
name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead.
- lpc replaced with ioport
All the changes below stem from this "simple" change.
I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!
TODO:
1. Change limitation in dtc that makes it hard to use hex in pci@
notation.
Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.
I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c,
so I suspect one of today's "clean up commits" broke something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
