SMBUS support for mcp55 and v3.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@724 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
5aabbccc93
commit
3b31e382a9
3 changed files with 298 additions and 1 deletions
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@ -20,7 +20,8 @@
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##
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \
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$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
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$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c \
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$(obj)/southbridge/nvidia/mcp55/stage1_smbus.o
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INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
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197
southbridge/nvidia/mcp55/mcp55_smbus.h
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197
southbridge/nvidia/mcp55/mcp55_smbus.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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* Copyright (C) 2006,2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/smbus_def.h>
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#define SMBHSTSTAT 0x1
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#define SMBHSTPRTCL 0x0
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x2
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#define SMBHSTDAT0 0x4
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#define SMBHSTDAT1 0x5
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/* Between 1-10 seconds, We should never timeout normally
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* Longer than this is just painful when a timeout condition occurs.
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*/
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#define SMBUS_TIMEOUT (100*1000*10)
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static inline void smbus_delay(void)
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{
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/* let's hope this is not optimized out */
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(void) intb(0x80);
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}
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static int smbus_wait_until_ready(u16 smbus_io_base)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(smbus_io_base + SMBHSTSTAT);
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val &= 0x1f;
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if (val == 0) {
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return 0;
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}
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outb(val,smbus_io_base + SMBHSTSTAT);
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} while(--loops);
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return -2;
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}
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static int smbus_wait_until_done(u16 smbus_io_base)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(smbus_io_base + SMBHSTSTAT);
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if ( (val & 0xff) != 0) {
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return 0;
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}
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} while(--loops);
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return -3;
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}
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static int do_smbus_recv_byte(u16 smbus_io_base, unsigned u8)
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{
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u8 global_status_register;
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u8 byte;
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
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smbus_delay();
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/* byte data recv */
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outb(0x05, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
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/* read results of transaction */
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byte = inb(smbus_io_base + SMBHSTCMD);
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if (global_status_register != 0x80) { // loose check, otherwise it should be 0
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return -1;
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}
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return byte;
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}
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static int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val)
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{
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u8 global_status_register;
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outb(val, smbus_io_base + SMBHSTDAT0);
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smbus_delay();
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/* set the command... */
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outb(val, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
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smbus_delay();
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/* set up for a byte data write */
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outb(0x04, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
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if (global_status_register != 0x80) {
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return -1;
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}
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return 0;
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}
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static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
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{
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u8 global_status_register;
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u8 byte;
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
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smbus_delay();
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/* set the command/address... */
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outb(address & 0xff, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* byte data read */
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outb(0x07, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
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/* read results of transaction */
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byte = inb(smbus_io_base + SMBHSTDAT0);
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if (global_status_register != 0x80) { // lose check, otherwise it should be 0
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return -1;
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}
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return byte;
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}
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static int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val)
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{
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u8 global_status_register;
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outb(val, smbus_io_base + SMBHSTDAT0);
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smbus_delay();
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
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smbus_delay();
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outb(address & 0xff, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* set up for a byte data write */
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outb(0x06, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
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if (global_status_register != 0x80) {
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return -1;
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}
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return 0;
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}
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99
southbridge/nvidia/mcp55/stage1_smbus.c
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99
southbridge/nvidia/mcp55/stage1_smbus.c
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@ -0,0 +1,99 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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* Copyright (C) 2006,2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console.h>
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#include <io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include "mcp55.h"
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#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
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#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
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#define pci_read_config16(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
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#define pci_write_config16(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
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#include "mcp55_smbus.h"
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#define SMBUS0_IO_BASE 0x1000
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#define SMBUS1_IO_BASE (0x1000+(1<<8))
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/*SIZE 0x40 */
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static void enable_smbus(void)
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{
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u32 dev;
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dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
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#if 0
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if (dev == PCI_DEV_INVALID) {
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die("SMBUS controller not found\r\n");
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}
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printk(BIOS_DEBUG, "SMBus controller enabled\r\n");
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#endif
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/* set smbus iobase */
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pci_write_config32(0, dev, 0x20, SMBUS0_IO_BASE | 1);
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pci_write_config32(0, dev, 0x24, SMBUS1_IO_BASE | 1);
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/* Set smbus iospace enable */
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pci_write_config16(0, dev, 0x4, 0x01);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
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outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
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}
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static u8 smbus_recv_byte(u8 device)
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{
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return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
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}
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static u8 smbus_send_byte(u8 device,u8 val)
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{
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return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
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}
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static u8 smbus_read_byte(u8 device, u8 address)
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{
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return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
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}
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static u8 smbus_write_byte(u8 device, u8 address, u8 char val)
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{
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return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
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}
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static u8 smbusx_recv_byte(u8 smb_index, u8 device)
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{
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return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device);
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}
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static u8 smbusx_send_byte(u8 smb_index, u8 device, u8 char val)
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{
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return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val);
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}
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static u8 smbusx_read_byte(u8 smb_index, u8 device, u8 address)
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{
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return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address);
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}
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static u8 smbusx_write_byte(u8 smb_index, u8 device, u8 address, u8 char val)
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{
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return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val);
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}
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