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With this set of changes dbe62 gets to a FILO prompt.

Browse source 
Set manual settings for dbe62 PLL; the auto settings are giving
slightly wrong values

Add call to dumplxmsr in dbe62 initram main()

Change dumplxmsr to void parameter

Add dumplxmsrs function to geodelx raminit support code

Correct spelling of CAS.

The big one: set spd variables correctly.

The not so big one: there is a bug in com2 enable I don't understand.
For now comment out two offending lines. The cs5536 debug prints
should be reduced later.

Change fuctory to factory. It's funny but confusing.
This patch also takes into account carl-daniel and uwe's comments.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@649 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-04-04 03:31:39 +00:00
commit b2e1002d9d
3 changed files with 76 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

44
mainboard/artecgroup/dbe62/initram.c
View file

@ -33,9 +33,9 @@
#include <northbridge/amd/geodelx/raminit.h>
#include <spd.h>
#define MANUALCONF 0 /* Do automatic strapped PLL config */
#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
#define PLLMSRLO 0x02000030
#define MANUALCONF 1 /* Do manual strapped PLL config */
#define PLLMSRHI 0x000003d9 /* manual settings for the PLL */
#define PLLMSRLO 0x07de0080 /* from factory bios */
#define DIMM0 ((u8) 0xA0)
#define DIMM1 ((u8) 0xA2)
@ -53,25 +53,23 @@ struct spd_entry {
/* Save space by using a short list of SPD values used by Geode LX Memory init */
static const struct spd_entry spd_table[] = {
{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
{SPD_BANK_DENSITY, 0x40},
{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
{SPD_MEMORY_TYPE, 7},
{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
{SPD_NUM_BANKS_PER_SDRAM, 4},
{SPD_PRIMARY_SDRAM_WIDTH, 8},
{SPD_NUM_DIMM_BANKS, 1},
{SPD_NUM_COLUMNS, 0xa},
{SPD_NUM_ROWS, 13},
{SPD_REFRESH, 0x3a},
{SPD_SDRAM_CYCLE_TIME_2ND, 60},
{SPD_SDRAM_CYCLE_TIME_3RD, 75},
{SPD_tRAS, 40},
{SPD_tRFC, 0x4b},
{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40},
{SPD_tRAS, 0x2d},
{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
{SPD_MIN_RAS_TO_CAS_DELAY, 0x58},
{SPD_tRRD, 0x3c},
{SPD_tRP, 0x58},
{SPD_NUM_BANKS_PER_SDRAM, 0x4},
{SPD_NUM_COLUMNS, 0x8},
{SPD_NUM_DIMM_BANKS, 0x1},
{SPD_REFRESH, 0x82},
{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
{SPD_tRCD, 15},
{SPD_tRFC, 70},
{SPD_tRP, 15},
{SPD_tRRD, 10},
};
/**
@ -124,6 +122,8 @@ static void mb_gpio_init(void)
*/
int main(void)
{
void dumplxmsrs(void);
u8 smb_devices[] = {
DIMM0, DIMM1
};
@ -151,8 +151,12 @@ int main(void)
sdram_enable(DIMM0, DIMM1);
printk(BIOS_DEBUG, "done sdram enable\n");
dumplxmsrs();
/* Check low memory */
ram_check(0x00000000, 640*1024);
/* The RAM is working now. Leave this test commented out but
* here for reference.
* Note that the range 0x87000 will fail; that's the stack! */
/* ram_check(0x00000000, 640*1024);*/
printk(BIOS_DEBUG, "stage1 returns\n");
return 0;

38
northbridge/amd/geodelx/raminit.c
View file

@ -35,6 +35,42 @@ static const u8 num_col_addr[] = {
u8 spd_read_byte(u16 device, u8 address);
/**
* Dump key MSR values for RAM init. You can call this function and then use it to
* compare to a factory BIOS setting.
* @param level printk level
*/
void dumplxmsrs(void)
{
const static unsigned long msrs[] = {
MC_CF07_DATA,
MC_CF8F_DATA,
MC_CF1017_DATA,
GLCP_DELAY_CONTROLS,
MC_CFCLK_DBUG,
MC_CF_PMCTR,
GLCP_SYS_RSTPLL
};
const static char *msrnames[] = {
"MC_CF07_DATA",
"MC_CF8F_DATA",
"MC_CF1017_DATA",
"GLCP_DELAY_CONTROLS",
"MC_CFCLK_DBUG",
"MC_CF_PMCTR",
"PLL reg"
};
int i;
for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){
struct msr msr;
msr = rdmsr(msrs[i]);
printk(BIOS_DEBUG, "(%lx): %x.%x\n", msrs[i], msr.hi, msr.lo);
}
}
/**
* Halt and Catch Fire. Print an error, then loop, sending NULLs on
* serial port, to ensure the message is visible.
@ -387,7 +423,7 @@ static void set_cas(u8 dimm0, u8 dimm1)
hlt();
}
printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;

16
southbridge/amd/cs5536/cs5536.c
View file

@ -258,6 +258,7 @@ static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
/* COM1 */
if (sb->com1_enable) {
printk(BIOS_SPEW, "uarts_init: enable COM1\n");
/* Set the address. */
switch (sb->com1_address) {
case 0x3F8:
@ -308,6 +309,7 @@ static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
wrmsr(MDD_UART1_CONF, msr);
} else {
/* Reset and disable COM1. */
printk(BIOS_SPEW, "uarts_init: disable COM1\n");
msr = rdmsr(MDD_UART1_CONF);
msr.lo = 1; /* Reset */
wrmsr(MDD_UART1_CONF, msr);
@ -322,6 +324,7 @@ static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
/* COM2 */
if (sb->com2_enable) {
printk(BIOS_SPEW, "uarts_init: enable COM2\n");
switch (sb->com2_address) {
case 0x3F8:
addr = 7;
@ -348,14 +351,20 @@ static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
/* GPIO3 - UART2_RX */
/* Set: Output Enable (0x4) */
outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
/* GPIO4 - UART2_TX */
/* Set: Input Enable (0x20) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
/* Set: INAUX1 Select (0x34) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
/* this totally disables com2 for serial, leave it out until we can
* figure it out
*/
// outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT);
// printk(BIOS_SPEW, "uarts_init: set INAUX2 for COM2\n");
/* Set: GPIO 3 + 3 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET,
@ -369,7 +378,9 @@ static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0;
wrmsr(MDD_UART2_CONF, msr);
printk(BIOS_SPEW, "uarts_init: COM2 enabled\n");
} else {
printk(BIOS_SPEW, "uarts_init: disable COM2\n");
/* Reset and disable COM2. */
msr = rdmsr(MDD_UART2_CONF);
msr.lo = 1; /* Reset */
@ -621,10 +632,13 @@ static void southbridge_init(struct device *dev)
uarts_init(sb);
if (sb->enable_gpio_int_route) {
printk(BIOS_SPEW, "cs5536: call vr_write\n");
vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
(sb->enable_gpio_int_route & 0xFFFF));
printk(BIOS_SPEW, "cs5536: done first call vr_write\n");
vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
(sb->enable_gpio_int_route >> 16));
printk(BIOS_SPEW, "cs5536: done second call vr_write\n");
}
printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",