coreboot/southbridge
Ronald G. Minnich dba27d1bcd This patch gets usb port 3 on dbe62 working and sets up a dts-based way to map
USB EHCI power control registers to power enables pins 1 and 2. 

Why doesn't port 4 work? Who knows. That's a problem for another day. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>


Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@688 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-03 15:22:16 +00:00
..
amd/cs5536 This patch gets usb port 3 on dbe62 working and sets up a dts-based way to map 2008-06-03 15:22:16 +00:00
intel/i82371eb This started out as a trivial change and turned into a big change. This 2008-02-16 04:13:44 +00:00