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Fix up references to pci functions now in stage 0.

Browse source 
Remove stage1.h -- not needed. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@763 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-14 16:16:07 +00:00
commit 61e04287b8
11 changed files with 66 additions and 93 deletions
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10
southbridge/nvidia/mcp55/ide.c
View file

@ -41,7 +41,7 @@ static void ide_init(struct device *dev)
u16 word;
u8 byte;
word = pci_read_config16(dev, 0x50);
word = pci_conf1_read_config16(dev, 0x50);
/* Ensure prefetch is disabled */
word &= ~((1 << 15) | (1 << 13));
if (conf->ide1_enable) {
@ -56,15 +56,15 @@ static void ide_init(struct device *dev)
word |= (1<<12);
word |= (1<<14);
pci_write_config16(dev, 0x50, word);
pci_conf1_write_config16(dev, 0x50, word);
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
pci_conf1_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
dword = pci_conf1_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
pci_conf1_write_config32(dev, 0xf8, dword);
#ifdef CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif

34
southbridge/nvidia/mcp55/lpc.c
View file

@ -144,10 +144,10 @@ static void lpc_common_init(struct device *dev, int master)
u32 dword;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte = pci_conf1_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
pci_conf1_write_config8(dev, 0x74, byte);
dword = pci_conf1_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
setup_ioapic(dword, master);
}
@ -162,8 +162,8 @@ static void enable_hpet(struct device *dev)
{
unsigned long hpet_address;
pci_write_config32(dev,0x44, 0xfed00001);
hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
pci_conf1_write_config32(dev,0x44, 0xfed00001);
hpet_address=pci_conf1_read_config32(dev,0x44)& 0xfffffffe;
printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address);
}
#endif
@ -180,20 +180,20 @@ static void lpc_init(struct device *dev)
#warning posted memory write enable disabled in mcp55 lpc?
#if 0
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
byte = pci_conf1_read_config8(dev, 0x46);
pci_conf1_write_config8(dev, 0x46, byte | (1<<0));
#endif
/* power after power fail */
#if 1
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte = pci_conf1_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
pci_conf1_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
#endif
/* Throttle the CPU speed down for testing */
@ -202,7 +202,7 @@ static void lpc_init(struct device *dev)
if(on) {
u16 pm10_bar;
u32 dword;
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
pm10_bar = (pci_conf1_read_config16(dev, 0x60)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
@ -213,16 +213,16 @@ static void lpc_init(struct device *dev)
#if 0
// default is enabled
/* Enable Port 92 fast reset */
byte = pci_read_config8(dev, 0xe8);
byte = pci_conf1_read_config8(dev, 0xe8);
byte |= ~(1 << 3);
pci_write_config8(dev, 0xe8, byte);
pci_conf1_write_config8(dev, 0xe8, byte);
#endif
/* Enable Error reporting */
/* Set up sync flood detected */
byte = pci_read_config8(dev, 0x47);
byte = pci_conf1_read_config8(dev, 0x47);
byte |= (1 << 1);
pci_write_config8(dev, 0x47, byte);
pci_conf1_write_config8(dev, 0x47, byte);
/* Set up NMI on errors */
byte = inb(0x70); // RTC70
@ -286,7 +286,7 @@ static void mcp55_lpc_enable_childrens_resources(struct device *dev)
int i;
int var_num = 0;
reg = pci_read_config32(dev, 0xa0);
reg = pci_conf1_read_config32(dev, 0xa0);
for (link = 0; link < dev->links; link++) {
struct device *child;
@ -324,9 +324,9 @@ static void mcp55_lpc_enable_childrens_resources(struct device *dev)
}
}
}
pci_write_config32(dev, 0xa0, reg);
pci_conf1_write_config32(dev, 0xa0, reg);
for(i=0;i<var_num;i++) {
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
pci_conf1_write_config32(dev, 0xa8 + i*4, reg_var[i]);
}

30
southbridge/nvidia/mcp55/mcp55.c
View file

@ -52,7 +52,7 @@ static struct device *find_lpc_dev( struct device *dev, unsigned devfn)
(lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
) ) {
u32 id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
id = pci_conf1_read_config32(lpc_dev, PCI_VENDOR_ID);
if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
) {
@ -82,7 +82,7 @@ static void mcp55_enable(struct device *dev)
/* sorry. Again, anonymous unions etc. would make this easier. */
if(dev->id.pci.device==0x0000) {
vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
vendorid = pci_conf1_read_config32(dev, PCI_VENDOR_ID);
deviceid = (vendorid>>16) & 0xffff;
// vendorid &= 0xffff;
} else {
@ -180,14 +180,14 @@ static void mcp55_enable(struct device *dev)
if(!sm_dev) return;
if ( sm_dev ) {
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4);
if (!dev->enabled) { //disable it
reg |= (1<<index2);
}
if (reg != reg_old) {
pci_write_config32(sm_dev, 0xe4, reg);
pci_conf1_write_config32(sm_dev, 0xe4, reg);
}
}
@ -199,14 +199,14 @@ static void mcp55_enable(struct device *dev)
if ( index == 0) { // for LPC
// expose ioapic base
byte = pci_read_config8(lpc_dev, 0x74);
byte = pci_conf1_read_config8(lpc_dev, 0x74);
byte |= ((1<<1)); // expose the BAR
pci_write_config8(dev, 0x74, byte);
pci_conf1_write_config8(dev, 0x74, byte);
// expose trap base
byte = pci_read_config8(lpc_dev, 0xdd);
byte = pci_conf1_read_config8(lpc_dev, 0xdd);
byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
pci_write_config8(dev, 0xdd, byte);
pci_conf1_write_config8(dev, 0xdd, byte);
return;
@ -216,16 +216,16 @@ static void mcp55_enable(struct device *dev)
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
final_reg = pci_read_config32(sm_dev, 0xe8);
final_reg = pci_conf1_read_config32(sm_dev, 0xe8);
final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
pci_conf1_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
#if 0
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4);
// reg |= (1<<0);
reg &= ~(0x3f<<4);
if (reg != reg_old) {
printk_debug("mcp55.c pcie enabled\n");
pci_write_config32(sm_dev, 0xe4, reg);
pci_conf1_write_config32(sm_dev, 0xe4, reg);
}
#endif
}
@ -238,9 +238,9 @@ static void mcp55_enable(struct device *dev)
if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
reg_old = pci_read_config32(sm_dev, 0xe8);
reg_old = pci_conf1_read_config32(sm_dev, 0xe8);
if (final_reg != reg_old) {
pci_write_config32(sm_dev, 0xe8, final_reg);
pci_conf1_write_config32(sm_dev, 0xe8, final_reg);
}
}
@ -251,7 +251,7 @@ static void mcp55_enable(struct device *dev)
void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
pci_conf1_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}

14
southbridge/nvidia/mcp55/pci.c
View file

@ -43,23 +43,23 @@ static void pci_init(struct device *dev)
#endif
/* System error enable */
dword = pci_read_config32(dev, 0x04);
dword = pci_conf1_read_config32(dev, 0x04);
dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */
pci_write_config32(dev, 0x04, dword);
pci_conf1_write_config32(dev, 0x04, dword);
#if 1
//only need (a01,xx]
word = pci_read_config16(dev, 0x48);
word = pci_conf1_read_config16(dev, 0x48);
word |= (1<<0); /* MRL2MRM */
word |= (1<<2); /* MR2MRM */
pci_write_config16(dev, 0x48, word);
pci_conf1_write_config16(dev, 0x48, word);
#endif
#if 1
dword = pci_read_config32(dev, 0x4c);
dword = pci_conf1_read_config32(dev, 0x4c);
dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
pci_write_config32(dev, 0x4c, dword);
pci_conf1_write_config32(dev, 0x4c, dword);
#endif
#ifdef CONFIG_PCI_64BIT_PREF_MEM
@ -84,7 +84,7 @@ static void pci_init(struct device *dev)
printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
#endif
printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); //TOM
pci_conf1_write_config32(dev, 0x50, dword); //TOM
}

4
southbridge/nvidia/mcp55/pcie.c
View file

@ -39,10 +39,10 @@ static void pcie_init(struct device *dev)
u32 dword;
/* System error enable */
dword = pci_read_config32(dev, 0x04);
dword = pci_conf1_read_config32(dev, 0x04);
dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */
pci_write_config32(dev, 0x04, dword);
pci_conf1_write_config32(dev, 0x04, dword);
}

8
southbridge/nvidia/mcp55/sata.c
View file

@ -40,7 +40,7 @@ static void sata_init(struct device *dev)
struct southbridge_nvidia_mcp55_sata_config *conf =
(struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration;
dword = pci_read_config32(dev, 0x50);
dword = pci_conf1_read_config32(dev, 0x50);
/* Ensure prefetch is disabled */
dword &= ~((1 << 15) | (1 << 13));
if(conf) {
@ -62,11 +62,11 @@ static void sata_init(struct device *dev)
dword &= ~(0x1f<<24);
dword |= (0x15<<24);
#endif
pci_write_config32(dev, 0x50, dword);
pci_conf1_write_config32(dev, 0x50, dword);
dword = pci_read_config32(dev, 0xf8);
dword = pci_conf1_read_config32(dev, 0xf8);
dword |= 2;
pci_write_config32(dev, 0xf8, dword);
pci_conf1_write_config32(dev, 0xf8, dword);
}
struct device_operations mcp55_sata = {

13
southbridge/nvidia/mcp55/stage1.c
View file

@ -27,7 +27,6 @@
#include <cpu.h>
#include <amd/k8/k8.h>
#include "mcp55.h"
#include "stage1.h"
#warning fix disgusting define of MCP55_NUM it is mainboard dependent
#define MCP55_NUM 1
@ -148,9 +147,9 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anac
u32 dword;
int i;
u32 bdf = PCI_BDF(busnx, devnx+1, 1);
dword = pci_read_config32(bdf, 0xe4);
dword = pci_conf1_read_config32(bdf, 0xe4);
dword |= 0x3f0; // disable it at first
pci_write_config32(bdf, 0xe4, dword);
pci_conf1_write_config32(bdf, 0xe4, dword);
for(i=0; i<3; i++) {
tgio_ctrl = inl(anactrl_io_base + 0xcc);
@ -172,9 +171,9 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anac
// wait 100us
udelay(100);
dword = pci_read_config32(bdf, 0xe4);
dword = pci_conf1_read_config32(bdf, 0xe4);
dword &= ~(0x3f0); // enable
pci_write_config32(bdf, 0xe4, dword);
pci_conf1_write_config32(bdf, 0xe4, dword);
// need to wait 100ms
udelay(100000);
@ -397,7 +396,7 @@ int mcp55_early_setup_x(void)
u32 id;
u32 bdf;
bdf = PCI_BDF(busnx, devnx, 0);
id = pci_read_config32(bdf, PCI_VENDOR_ID);
id = pci_conf1_read_config32(bdf, PCI_VENDOR_ID);
if(id == 0x036910de) {
busn[mcp55_num] = busnx;
devn[mcp55_num] = devnx;
@ -434,7 +433,7 @@ unsigned int get_sbdn(unsigned int bus)
/* Find the device.
*/
u32 bdf;
if (!pci_locate_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) {
if (!pci_conf1_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) {
die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\r\n");
}

24
southbridge/nvidia/mcp55/stage1.h
View file

@ -1,24 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define pci_read_config32(bdf, where) pci_cf8_conf1.read32(bdf, where)
#define pci_write_config32(bdf, where, what) pci_cf8_conf1.write32(bdf, where, what)
#define pci_read_config16(bdf, where) pci_cf8_conf1.read32(bdf, where)
#define pci_write_config16(bdf, where, what) pci_cf8_conf1.write32(bdf, where, what)
#define pci_locate_device(vid, did, slot) pci_cf8_conf1.find(vid, did, slot)

9
southbridge/nvidia/mcp55/stage1_smbus.c
View file

@ -27,7 +27,6 @@
#include <device/device.h>
#include <device/pci.h>
#include "mcp55.h"
#include "stage1.h"
#include "mcp55_smbus.h"
#define SMBUS0_IO_BASE 0x1000
@ -192,16 +191,16 @@ int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val)
void enable_smbus(void)
{
u32 bdf;
if (!pci_locate_device(0x10de, 0x0368, &bdf)) {
if (!pci_conf1_find_device(0x10de, 0x0368, &bdf)) {
die("SMBUS controller not found\r\n");
}
printk(BIOS_DEBUG, "SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(bdf, 0x20, SMBUS0_IO_BASE | 1);
pci_write_config32(bdf, 0x24, SMBUS1_IO_BASE | 1);
pci_conf1_write_config32(bdf, 0x20, SMBUS0_IO_BASE | 1);
pci_conf1_write_config32(bdf, 0x24, SMBUS1_IO_BASE | 1);
/* Set smbus iospace enable */
pci_write_config16(bdf, 0x4, 0x01);
pci_conf1_write_config16(bdf, 0x4, 0x01);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);

9
southbridge/nvidia/mcp55/stage1_usbdebug.c
View file

@ -33,15 +33,14 @@
#define EHCI_DEBUG_OFFSET 0x98
#include "pci.h"
#include "stage1.h"
static void set_debug_port(unsigned port)
{
u32 dword;
u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1);
dword = pci_read_config32(bdf, 0x74);
dword = pci_conf1_read_config32(bdf, 0x74);
dword &= ~(0xf<<12);
dword |= (port<<12);
pci_write_config32(bdf, 0x74, dword);
pci_conf1_write_config32(bdf, 0x74, dword);
}
@ -49,7 +48,7 @@ static void mcp55_enable_usbdebug_direct(unsigned port)
{
u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1);
set_debug_port(port);
pci_write_config32(bdf, EHCI_BAR_INDEX, EHCI_BAR);
pci_write_config8(bdf, 0x04, 0x2); // mem space enable
pci_conf1_write_config32(bdf, EHCI_BAR_INDEX, EHCI_BAR);
pci_conf1_write_config8(bdf, 0x04, 0x2); // mem space enable
}

4
southbridge/nvidia/mcp55/usb2.c
View file

@ -41,9 +41,9 @@
static void usb2_init(struct device *dev)
{
u32 dword;
dword = pci_read_config32(dev, 0xf8);
dword = pci_conf1_read_config32(dev, 0xf8);
dword |= 40;
pci_write_config32(dev, 0xf8, dword);
pci_conf1_write_config32(dev, 0xf8, dword);
}
static void usb2_set_resources(struct device *dev)