When parsing "extensions", we should skip the first EDID (main) block and start
from offset 128 (EDID may have only main block, so an EDID without any
extension is fine) because the header format for main block and extensions are
different.
Without this we will see "Unknown extension block" on all EDIDs, and seeing a
error (1) return value for EDIDs without extension.
Also, after the first "unknown" error is fixed, we can now collect all return
values from parse_extension, and give error when any of the extensions are wrong
(not just last one).
BRANCH=none
BUG=chrome-os-partner:25933
TEST=emerge-nyan coreboot chromeos-bootimage
Manually boot on Nyan and no "Unknown extension block" anymore.
Also tried EDID from following devices: Link, Peppy. Display panel
initialization is still functional.
Change-Id: I0ee029ac8ec6800687cd7749e23989399e721109
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193011
To set the 8 different BCT as hynix-2GB-204 first. Once the
corresponding BCT release from AE, change it.
BRANCH=none
BUG=None
TEST=emerge-nyan_blaze coreboot builds OK
Signed-off-by: Neil Chen <neilc@nvidia.com>
Change-Id: Ia42a4a5b85c561421ab8ae9aaf21c46a3c0a3513
Reviewed-on: https://chromium-review.googlesource.com/191682
Tested-by: Neil Chen <neilc@nvidia.com>
Reviewed-by: Artiste Hsu <chhsu@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Neil Chen <neilc@nvidia.com>
The EC doesn't seem to be able to handle its bus running at 4 MHz or higher.
To avoid it not being able to keep up, we reduce the frequency of that bus on
all nyan derivatives to 3 MHz. Because PLLP can't be divided that low, we
switch the clock source to CLKM.
BUG=chrome-os-partner:22849
TEST=Built and booted on nyan.
BRANCH=None
Change-Id: I8f31b41098d64634427b4686f5333012f643fada
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/193349
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Consolidate the register setting clrsetbits_le32 call to simplify the macros.
Add a check for bits of the divisor being dropped. The clock source registers
will throw away bits that aren't supported, so we can check for divisor
overflow by checking for dropped bits.
BUG=None
TEST=Purposefully tried to set a clock to a rate which overflows its divisor.
Verified that the check triggered. Booted on nyan. Verified the TPM i2c bus
frequency was still correct.
BRANCH=None
Change-Id: I3b1b6ba57f6b7729f303d15a16b685a48751d41f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/193348
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
To ensure that the command1 write which sets the "go" bit completes before
other reads to the device. Otherwise, there's a race condition where those
register values might still have their values from the last transfer. With
different SPI clock frequencies, that could lead to spi_delay being told there
were negative bytes still to send. Its expected delay would wrap to a negative
value, that was passed to udelay, and the system would sit there for 4 seconds
not doing anything.
BUG=None
TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was
causing the 4+ second delay and verified that it no longer happened.
BRANCH=None
Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/193347
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This fixes two problems with the clock configuration on tegra124. First, the
macro which set up the i2c clocks tried to account for the fact that the i2c
divisor's lsb represents 1.0 where it normally represents 0.5 by multiplying
the target frequency by 2. That doesn't work, unfortunately, because the
divisor is actually n + 1, and what n + 1 means depends on where the one's
place is in the divisor.
Also, when calculating the divisor, the standard C division operator uses
truncation to deal any remainder which tends to make the divisor smaller. That
has the effect of making the output frequency higher than what was requested.
Since it's usually safer to undershoot a frequency than overshoot it, this
change makes those divisions round up instead.
Finally, the hand tuned temporary UART clock configuration was adjusted so
that it still ends up with the same divisor. Without that, very early output
from the bootblock is garbled, specifically the coreboot welcome banner,
build timestamp, etc.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan. Used a logic analyzer to verify that the TPM
i2c bus ran at 400KHz instead of 660KHz, and that the divisor was the expected
value. Measured boot time with and without EFS and verified that there was no
change. Spot checked the output for errors and verified that none of the
bootblock output was garbled.
BRANCH=None
Change-Id: I7e948c361ed4bf58c608627d32f2e3424faea1fb
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/193362
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
To read EDID, we need to access I2C via DP AUX channel.
BRANCH=none
BUG=chrome-os-partner:25933
TEST=emerge-nyan coreboot chromeos-bootimage
Change-Id: I2666b5d46843485b79265a537f19bd8eab5e1a26
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188858
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Turns out that when you clear 28 bits starting with bit 3, you leave bit
31 standing. Ooops...
This shouldn't really matter since that bit is reserved/SBZ in CLIDR
anyway, but it's still nice to fix it. This whole thing should really be
an AND for clarity anyway in my opinion.
Bug found in upstream NetBSD (who would've thought...).
BUG=None
TEST=Still boots.
Change-Id: Ic826e82d58fd1ce984971afea3dfa9296f746d9f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193300
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Some lines in decode_edid have incorrect indent levels.
BUG=none
TEST=emerge-nyan coreboot
BRANCH=none
Change-Id: Icc9cb57ff8dd2e2056599b3dc733fe5ac4e41c16
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193010
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Provide the option to embed MRC as an ELF file and not just
binary blob. This allows for MRC to be relocated.
BUG=chrome-os-partner:27654
BRANCH=rambi
TEST=Built and booted rambi.
Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192893
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds the 10ms TRSTRCY delay between a reset and the following
Set Address command that is required by the USB 2.0 specification to the
EHCI root hub driver. The generic_hub driver that's used for XHCI and
external hubs already included this delay. This is such a glaring
violation of the spec that I'm really amazed how many USB 2.0 devices
we tested before seemed perfectly fine with responding to a Set Address
within 2 microframes of the reset...
It also increases the port reset hold delay by one millisecond to avoid
an ugly race condition on Tegra SoCs: they decided to time the 50ms
themselves instead of relying on the CPU to do it (fair enough), and to
automatically transition Port Reset to 0 and Port Enable to 1 after that
(bad idea). If the CPU's read-modify-write to clear Port Reset races
exactly with the host controller setting Port Enable, we may end up
clearing the bit again and going into the companion controller handoff
path later on. The added millisecond shouldn't cause any problems for
other host controllers and is not a big deal compared to other delays in
this code path.
BUG=chrome-os-partner:26749
TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a
blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always
gets detected correctly.
Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189872
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Jim Lin <jilin@nvidia.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
If EFS is enabled and vboot didn't tell us it's going to use the display, we
can skip initializing it and save some boot time.
BUG=chrome-os-partner:27094
TEST=Built and booted on nyan without EFS in recovery mode and normal mode.
Built and booted on nyan with EFS in recovery mode and normal mode. Verified
that in normal mode with EFS the display initialization was skipped and boot
time was essentially the same as when display initialization was simply
commented out.
BRANCH=None
Change-Id: I1e2842b57a38061f40514407c8fab1e38b75be80
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192544
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Though vboot could be built for arm platforms the resulting
code was not being included in the cbfs. Now conditionally
include the vboot rmdoule like x86.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built nyan with vboot. Confirmed being added to cbfs.
Change-Id: I677d0bf16dc488cf2d5b75dd1a65cf123d3ad9d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190927
In order to build rmodules for armv7 boards, the default
compiler options need to be set so the assembler sources
can correclty compile. For now assume rmodules for arm
devices use the ramstage compiler options.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built vboot as rmodule for nyan.
Change-Id: I8d12a2a57944b187cbdff2f22176de5b4de87a54
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190926
The non-x86 systems need the monotonic timer interface.
Add tegra124's timer implementation so vboot can link.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built nyan with vboot verfication.
Change-Id: I75b99b6e07eeab0324495f97472f14a36883161e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190925
Depending on the platform the underlying regions vboot requires
may not be accessible through a memory-mapped interface. Allow
for non-memory-mapped regions by providing a region request
abstraction. There is then only a few touch points in the code to
provide compile-time decision making no how to obtain a region.
For the vblocks a temporary area is allocated from cbmem. They
are then read from the SPI into the temporarily buffer.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built and booted a rambi with vboot verification.
Change-Id: I828a7c36387a8eb573c5a0dd020fe9abad03d902
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190924
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
- Remove the call to clear_stall in xhci_reset_endpoint because we will
call clear_stall from the mass-storage driver.
- Remove the xhci_reset_endpoint call from xhci_bulk on STALL since we
will reset on the next transfer anyway.
- Remove the clear_halt parameter from xhci_bulk since it's now unused.
BUG=chrome-os-partner:26687
TEST=Manual on Rambi w/ USB_DEBUG enabled in libpayload. Boot with SanDisk
Extreme USB 3.0 drive in USB 3.0 port, verify that after STALL is
encountered reset succeeds and device is initialized without extra
delay.
BRANCH=Rambi
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I852b87621861109e596ec24b78a8f036d796ff14
Reviewed-on: https://chromium-review.googlesource.com/192866
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Whenever spi_xfer is called and whenver it's implemented, the natural unit for
the amount of data being transfered is bytes. The API expected things to be
expressed in bits, however, which led to a lot of multiplying and dividing by
eight, and checkes to make sure things were multiples of eight. All of that
can now be removed.
BUG=None
TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
errors in the firmware log. Built for rambi.
BRANCH=None
Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192049
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
They were only used internal to the SPI drivers and, according to the comment
next to their prototypes, were for when the SPI controller doesn't control the
chip select line directly and needs some help.
BUG=None
TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan.
BRANCH=None
Change-Id: If4622819a4437490797d305786e2436e2e70c42b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192048
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
These constants aren't used anywhere.
BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None
Change-Id: Ifdad9b088a281909892edb34dcb58419e0e123ba
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192047
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The spi_flash_probe and and spi_setup_slave functions each took a max_hz
parameter and a spi_mode parameter which were never used.
BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None
Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192046
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The mp_init library was based off of haswell code, but baytrail
was the first chipset to take advantage of it. Move haswell over
to using it so that the code duplication can be removed.
BRANCH=None
BUG=None
TEST=Built and booted falco. Suspend and resume tested.
Change-Id: I54bb8ab70adc0b19d4c329b47504106aa4546698
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/191955
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This is a companion patch of CL:191692 "Tegra: Fix Beep".
TEST=Booted Big. Verified beeps at dev screen. Measured frequency by smartphone.
Built Blaze.
BUG=chrome-os-partner:26609
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I9ba47d06202e9968a908c4a15cfbeac4bfe2c20c
Reviewed-on: https://chromium-review.googlesource.com/192063
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
The vboot implementation previously assumed that ramstage would
be a relocatable module. Allow for ramstage not being a relocatable
module.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built nyan with vboot.
Change-Id: Id3544533740d77e2db6be3960bef0c129173bacc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190923
Reviewed-by: Gabe Black <gabeblack@chromium.org>
The arm architecture currently exports cache_sync_instructions()
in <arch/cache.h>. In order for rmodule loading to work on arm
architectures the cache_sync_instructions() needs to be called to
sequence the instruction cache. To avoid sprinkling #ifdefs around
just add an empty cache_sync_instructions() definition.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built and booted nyan and rambi.
Change-Id: I1a969757fffe0ca92754a0d953ba3630810556e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/191551
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Add support for creating ARM rmodules. There are 3 expected
relocations for an ARM rmodule:
- R_ARM_ABS32
- R_ARM_THM_PC22
- R_ARM_THM_JUMP24
R_ARM_ABS32 is the only type that needs to emitted for relocation
as the other 2 are relative relocations.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built vbootstub for ARM device.
Change-Id: I0c22d4abca970e82ccd60b33fed700b96e3e52fb
Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Reviewed-on: https://chromium-review.googlesource.com/190922
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
The TPM now works correctly with the I2C bus running at 400 KHz. Running it at
that frequency saves some boot time.
CQ-DEPEND=CL:191634
CQ-DEPEND=CL:191793
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with and without EFS.
BRANCH=None
Change-Id: I157308c2745342dc1ada4499433004c7ce1c6435
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191813
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Not doing so makes it fail when run at high frequency.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with EFS and with the TPM turned up to 400 KHz.
BRANCH=None
Change-Id: I1cfb69c55f03cb90f66f437289803d897a1aad5c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191812
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the only way to clear the error bits in the controller. Without
clearing them, every future transaction will look like it failed.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with the TPM frequency turned up to 400 KHz.
BRANCH=None
Change-Id: Ib654e60ec3039ad9f5f96aa7288d3d877e5c843a
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191811
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Currently we put the VPR write code just right before the AVP is going
to freeze. We have no idea does the write operation successful or not
before halting the AVP. And the power_on_main_cpu should be the last step
of that. So we make a fix to change the order.
BUG=none
BRANCH=none
TEST=LP0 suspend stress test and check the VPR is correct;
LP0 suspend stress test with video playback
Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/192029
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Tom Warren <twarren@nvidia.com>
Tested-by: Tom Warren <twarren@nvidia.com>
These make it possible to reset peripherals without having to dig into the
crc.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with EFS and with the TPM bus turned up to
400KHz.
BRANCH=None
Change-Id: I7e77b719e1ba30d2964cfbfda467f937d80b5b21
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191810
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
spi_set_speed was never implemented, and spi_cs_is_valid was only implemented
as a stub and never called.
BUG=None
TEST=Built for rambi, falco, and peach_pit.
BRANCH=None
Change-Id: If30c2339f5e0360a5099eb540fab73fb23582905
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192045
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is required to send 1.5Mhz clock to Max98090 and get a right beep sound.
BUG=chrome-os-partner:26609
TEST=Booted Nyan. Verified Max98090 can beep. Measured frequency by smartphone.
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ie3ff6df6759cb23d78dc05069553ddb4eb8e508a
Reviewed-on: https://chromium-review.googlesource.com/191791
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
To enable EFS, we need to be able to talk to the TPM and the EC before the RAM
stage starts. That means we need to set up the pins for those busses, clock
those controllers and take them out of reset.
BUG=None
TEST=Built for nyan, nyan_big, and nyan_blaze. Booted on nyan. With other
changes which implement EFS on nyan, saw EC and TPM communication work when in
vboot.
BRANCH=None
Change-Id: Ic65d69fd42beec5f03084c8cb970927c2f69dfb6
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191390
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The SPI drivers for tegra and exynos5420 have code in them which waits for a
frame header and leaves filler data out. The SPI driver shouldn't have support
for frame headers directly. If a device uses them, it should support them
itself. That makes the SPI drivers simpler and easier to write.
When moving the frame handling logic into the EC support code, EC communication
continued to work on tegra but no longer worked on exynos5420. That suggested
the SPI driver on the 5420 wasn't working correctly, so I replaced that with
the implementation in depthcharge. Unfortunately that implementation doesn't
support waiting for a frame header for the EC, so these changes are combined
into one.
BUG=None
TEST=Built and booted on pit. Built and booted on nyan. In both cases,
verified that there were no error messages from the SPI drivers or the EC
code.
BRANCH=None
Change-Id: I62a68820c632f154acece94f54276ddcd1442c09
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191192
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The display code for the tegra124 was cleaned up recently, but only the nyan
device tree was updated to match the new code, not big's or blaze's. This
change copies nyan's device tree over to those other two boards which will get
them building again. The settings may not be correct, but they'll be no less
correct than they were before. I also updated the copyright date for nyan.
BUG=none
TEST=Built for nyan, nyan_big, nyan_blaze. Booted on nyan_big and verified the
panel wasn't damaged by the new display code or settings.
BRANCH=None
Change-Id: I75055a01f9402b3a9de9a787a9d3e737d25bb515
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191364
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Create a reserved memory resource for range 0xc0000-0xfffff
where reside the VGA ROM (at 0xc0000) and ACPI root pointer
(at 0xfda80) so that depthcharge does not wipe these needed
structures during initialization.
BUG=None
BRANCH=none
TEST=Boot CrOS from depthcharge, VGA and ACPI are functional
Change-Id: Ic741dbb6766a1b0a16744d8d5288c8840379a8c5
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/191098
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The existing display init functions were translated from a script. The new
code will play the same functions but are cleaner and readable and easier to
be ported to new panel.
BUG=none
TEST=build nyan and boot up kernel.
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: Ic9983e57684a03e206efe3731968ec62905f4ee8
Reviewed-on: https://chromium-review.googlesource.com/189518
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Initial SCTLR setup done in arm_init_caches for EL3 is now
copied when switching to EL2.
BUG=None
BRANCH=none
TEST=Run coreboot and check for correct SCTLR_EL2 value
Change-Id: I88942ae913cb80c5ca561e5bdd790732dc3348d7
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187468
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The cbmem implementation isn't supported on anything other than x86 right now
and actually causes memory corruption on ARM machines. Until that's fixed, this
will prevent people from turning it on and causing hard to track down errors.
BUG=None
TEST=Built for rambi and verified that CONSOLE_CBMEM was still enabled. Built
for nyan and verified that it still wasn't.
BRANCH=None
Change-Id: I00e8aacf008acfe2f76d4eab82570f7c1cc89cab
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191107
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Support for it is broken on ARM and causes memory corruption.
BUG=None
TEST=Built and booted on nyan. Built for daisy, nyan_big and peach_pit.
BRANCH=None
Change-Id: If62c8a4b253ea996f84aa1ce7f789c80bd8d2b9f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191106
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This adds chromeos.c file which configures chromeos GPIOs for the
gizmo board. SPI_WP, REC_MODE and DVP_MODE are mapped to GPIO_A,
GPIO_B and GPIO_C input pins on the explorer board, respectively.
Power button is detected through AcpiPmEvtBlk registers and
lid switch is hardcoded to open.
BUG=none
BRANCH=none
TEST=Test with printk each GPIO, run depthcharge with REC_MODE on
Change-Id: Ie6c65e8a6114da09a24c19debb51f75d45e953c7
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190858
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
