nyan: Fix the build for big and blaze.
The display code for the tegra124 was cleaned up recently, but only the nyan device tree was updated to match the new code, not big's or blaze's. This change copies nyan's device tree over to those other two boards which will get them building again. The settings may not be correct, but they'll be no less correct than they were before. I also updated the copyright date for nyan. BUG=none TEST=Built for nyan, nyan_big, nyan_blaze. Booted on nyan_big and verified the panel wasn't damaged by the new display code or settings. BRANCH=None Change-Id: I75055a01f9402b3a9de9a787a9d3e737d25bb515 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/191364 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black
chrome-internal-fetch
parent
38e689a9a3
commit
ea235f23df
3 changed files with 81 additions and 39 deletions
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@ -1,7 +1,7 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2013 Google Inc.
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -28,9 +28,14 @@ chip soc/nvidia/tegra124
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "1366"
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register "yres" = "768"
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# this setting is what nvidia does; it makes no sense
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# and does not agree with hardware. Why'd they do it?
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register "framebuffer_bits_per_pixel" = "18"
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# bits per pixel and color depth
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register "framebuffer_bits_per_pixel" = "16"
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register "color_depth" = "6"
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# "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h
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register "panel_bits_per_pixel" = "18"
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register "cache_policy" = "DCACHE_WRITETHROUGH"
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# With some help from the mainbaord designer
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@ -40,12 +45,12 @@ chip soc/nvidia/tegra124
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register "panel_vdd_gpio" = "0"
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register "pwm" = "1"
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# taken from u-boot; these look wrong however.
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register "vdd_delay" = "400"
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register "vdd_data_delay" = "4"
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register "data_backlight_delay" = "203"
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register "backlight_pwm_delay" = "17"
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register "pwm_backlight_en_delay" = "15"
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# various panel delay time
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register "vdd_delay_ms" = "200"
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register "vdd_to_hpd_delay_ms" = "200"
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register "hpd_unplug_min_us" = "2000"
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register "hpd_plug_min_us" = "250"
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register "hpd_irq_min_us" = "250"
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# How to compute these: xrandr --verbose will give you this:
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#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
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@ -64,17 +69,33 @@ chip soc/nvidia/tegra124
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# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
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# h: width 1366 start 1502 end 1532 total 1592
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# v: height 768 start 776 end 788 total 800
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# These numbers were provided by Nvidia.
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register "href_to_sync" = "1"
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register "hfront_porch" = "44"
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register "hsync_width" = "46"
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register "hback_porch" = "44"
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register "href_to_sync" = "68"
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register "hfront_porch" = "136"
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register "hsync_width" = "30"
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register "hback_porch" = "60"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "6"
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register "vsync_width" = "8"
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register "vback_porch" = "6"
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register "vref_to_sync" = "4"
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register "vfront_porch" = "8"
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register "vsync_width" = "12"
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register "vback_porch" = "12"
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# we *know* the pixel clock for this system.
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register "pixel_clock" = "71"
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# 1592 x 800 x 60Hz = 76416000
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register "pixel_clock" = "76416000"
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register "pll_div" = "2"
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# use plld_out0 (ie, plld/2) as clock source
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# plld -> plld_out0 -> pclk
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# plld = plld_out0 * 2 = (pclk * pll_div) * 2
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# = 305664000Hz
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# link configurations
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register "lane_count" = "1"
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register "enhanced_framing" = "1"
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register "link_bw" = "10"
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# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
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register "drive_current" = "0x13131313"
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register "preemphasis" = "0x00000000"
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register "postcursor" = "0"
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end
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@ -28,9 +28,14 @@ chip soc/nvidia/tegra124
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "1366"
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register "yres" = "768"
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# this setting is what nvidia does; it makes no sense
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# and does not agree with hardware. Why'd they do it?
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register "framebuffer_bits_per_pixel" = "18"
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# bits per pixel and color depth
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register "framebuffer_bits_per_pixel" = "16"
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register "color_depth" = "6"
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# "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h
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register "panel_bits_per_pixel" = "18"
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register "cache_policy" = "DCACHE_WRITETHROUGH"
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# With some help from the mainbaord designer
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@ -40,12 +45,12 @@ chip soc/nvidia/tegra124
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register "panel_vdd_gpio" = "0"
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register "pwm" = "1"
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# taken from u-boot; these look wrong however.
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register "vdd_delay" = "400"
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register "vdd_data_delay" = "4"
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register "data_backlight_delay" = "203"
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register "backlight_pwm_delay" = "17"
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register "pwm_backlight_en_delay" = "15"
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# various panel delay time
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register "vdd_delay_ms" = "200"
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register "vdd_to_hpd_delay_ms" = "200"
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register "hpd_unplug_min_us" = "2000"
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register "hpd_plug_min_us" = "250"
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register "hpd_irq_min_us" = "250"
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# How to compute these: xrandr --verbose will give you this:
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#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
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@ -64,17 +69,33 @@ chip soc/nvidia/tegra124
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# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
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# h: width 1366 start 1502 end 1532 total 1592
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# v: height 768 start 776 end 788 total 800
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# These numbers were provided by Nvidia.
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register "href_to_sync" = "1"
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register "hfront_porch" = "44"
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register "hsync_width" = "46"
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register "hback_porch" = "44"
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register "href_to_sync" = "68"
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register "hfront_porch" = "136"
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register "hsync_width" = "30"
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register "hback_porch" = "60"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "6"
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register "vsync_width" = "8"
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register "vback_porch" = "6"
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register "vref_to_sync" = "4"
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register "vfront_porch" = "8"
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register "vsync_width" = "12"
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register "vback_porch" = "12"
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# we *know* the pixel clock for this system.
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register "pixel_clock" = "71"
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# 1592 x 800 x 60Hz = 76416000
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register "pixel_clock" = "76416000"
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register "pll_div" = "2"
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# use plld_out0 (ie, plld/2) as clock source
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# plld -> plld_out0 -> pclk
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# plld = plld_out0 * 2 = (pclk * pll_div) * 2
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# = 305664000Hz
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# link configurations
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register "lane_count" = "1"
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register "enhanced_framing" = "1"
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register "link_bw" = "10"
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# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
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register "drive_current" = "0x13131313"
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register "preemphasis" = "0x00000000"
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register "postcursor" = "0"
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end
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