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tegra124: fix the dangerous VPR write order

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Currently we put the VPR write code just right before the AVP is going
to freeze. We have no idea does the write operation successful or not
before halting the AVP. And the power_on_main_cpu should be the last step
of that. So we make a fix to change the order.

BUG=none
BRANCH=none
TEST=LP0 suspend stress test and check the VPR is correct;
     LP0 suspend stress test with video playback

Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/192029
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Tom Warren <twarren@nvidia.com>
Tested-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Joseph Lo 2014-03-28 19:13:51 +08:00 • committed by chrome-internal-fetch
commit 51473811fa
1 changed files with 2 additions and 2 deletions
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4
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
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@ -599,13 +599,13 @@ void lp0_resume(void)
config_tsc();
power_on_main_cpu();
// Disable VPR.
write32(0, mc_video_protect_size_mb_ptr);
write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
mc_video_protect_reg_ctrl_ptr);
power_on_main_cpu();
// Halt the AVP.
while (1)
write32(FLOW_MODE_STOP | EVENT_JTAG,