CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
for Broadwell, never took the devicetree config into account.
Rewrite the selection with the following in mind:
o cpu_is_ult() might return `true` for ULX SKUs, too,
o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
cooling, so leave that as devicetree option.
For Haswell, the following frequency selections are valid:
o ULX: 337.5MHz by default, 450MHz optional
o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
it wasn't selectable before either)
o others: 540MHz by default, 450MHz optional
For Broadwell:
o ULX: 450MHz by default, 337.5MHz / 540MHz optional
o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional
Side effects: A too high setting in the devicetree results in the
highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
instead of 450MHz.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2539a6b66b677217a2c5e44c4fe2fc7b8b5624bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e392f414cd
Original-Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/17768
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453358
SD card detect pins should normally have a pull-up. It seems that for
micro-SD cards this doesn't really matter all that much, but for the
full-size slots we have on some Oak-derivatives (like Hana) it does.
BRANCH=oak
BUG=b:35854317
TEST=Booted Hana, confirmed that card detect no longer seemed stuck-on.
Booted Elm and confirmed that SD card behavior didn't change.
Change-Id: I428ac92efb07f94265673b04e0e0dd452649b9fd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452861
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reserve the whole TZRAM area because it will be marked as secure-only
by BL31 and can not be accessed by the non-secure kernel.
CQ-DEPEND=CL:452659
BUG=chrome-os-partner:57361
BRANCH=firmware-gru-8785.B
TEST=the reserve memory is resized
Change-Id: I39c4cb530f41a7b0f7f3064125072dd85b62276f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/418102
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit ea9fe064a9b1e1ce81fca74f829a0fb6e78ce426)
Reviewed-on: https://chromium-review.googlesource.com/452640
Tested-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Without this change, error "Unknown descriptor version: 4" will be
returned if this frequency is selected (seen on GLKRVP)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic95473e14f12298827297abc17e066d3a9f35783
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 589fc3473e
Original-Change-Id: Ib5bfb996b85c7245d8f9c70988bfd5bbac882d74
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18688
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452897
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Skylake systems like Cave and Caroline.
This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.
BUG=b:35774937
BRANCH=none
TEST=update caroline coreboot and test i/o latency is under 100ms
Change-Id: I7ebb13c7f72279c9c1727f68e0ad96949715bf9a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d448a5e98b
Original-Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18532
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452896
Decode DDR2 SPD similar to DDR3 SPD decoder to ease
readability, reduce code complexity and reduce size of
maintainable code.
Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid
compilation errors.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2580a164627a0348da02aad6dbbe5311c442fe35
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e53ae6f5c
Original-Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18273
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452895
This configures GPIO_177 as an input pin for SDCARD card
detect. This also changes the ownership of the pin from ACPI
to GPIO driver.
Assign the sdcard card detect pin in devicetree for reef variants.
CQ-DEPEND=CL:448173
BUG=chrome-os-partner:63070
TEST=None
Change-Id: I6a146d62c0e7f6715d5b63180bfe8cd7f85dd56e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e4d12c5b1
Original-Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64
Original-Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18497
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452894
This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.
This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.
Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.
CQ-DEPEND=CL:448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.
Change-Id: I13a4250606be8adb7a180b4ec3f58e89f197101b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dd7b402d5
Original-Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Original-Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18496
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/452893
Address the iasl 20160108-64 (Ubuntu 16.04) warnings below.
```
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20160108-64
Copyright (c) 2000 - 2016 Intel Corporation
dsdt.aml 245: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 262: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 277: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 295: Method(_CRS, 0) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
```
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic33a018d9dc9b9acec079499684401da17177681
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4f92fa603
Original-Change-Id: Id5b0f33fba8ea25e4a6aa4f01c69a69aaf5aef23
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18323
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452892
The init files for the AMD families using the AGESA platform
initialization code are quite similar. So reduce the differences, by
using the same comments, variable names, console messages, and blank
lines.
BUG=none
BRANCH=none
TEST=none
Change-Id: I290453cd875ed445755de6218f9349bc9906e481
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 22f32c723c
Original-Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18507
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452891
cr50 by default delays nvmem commits internally from the point of
reset to accumulate change state. However, the factory process can
put a board into dev mode through the recovery screen. This state
is stored in the TPM's nvmem space. When the factory process is
complete a disable_dev_request and battery_cutoff_request is performed.
This leads to disabling the dev mode in TPM, but the battery is
subsequently cut off so the nvmem contents never stick. Therefore,
whenever antirollback_write_space_firmware() is called we know there
was a change in secdata so request cr50 to immediately enable nvmem
commits going forward. This allows state changes to happen immediately.
The fallout from this is that when secdata is changed that current
boot will take longer because every transaction that writes to TPM
nvmem space will perform a write synchronously. All subsequent boots
do not have that effect.
It should also be noted that this approach to the implementation is
a pretty severe layering violation. However, the current TPM APIs
don't lend themselves well to extending commands or re-using code
outside of the current routines which inherently assume all knowledge
of every command (in conflict with vendor commands since those are
vendor-specific by definition).
BUG=b:35775104
BRANCH=reef
TEST=Confirmed disablement of dev mode sticks in the presence of:
crossystem disable_dev_request=1; crossystem
battery_cutoff_request=1; reboot;
Change-Id: Ia2f5ec97f750570c3b16aa68b01ab1eaa94f6960
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eeb77379e0
Original-Change-Id: I3395db9cbdfea45da1f5cb994c6570978593b944
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18681
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452888
Going forward it's important to note when a CR50 is expected
to be present in the system. Additionally, this Kconfig addition
provides symmetry with the equivalent i2c Kconfig option.
BUG=b:35775104
Change-Id: I0c52abdf30620cd54be7f213eb41c1622f533743
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b9fc9e801
Original-Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18680
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452887
verstage can be pretty chatty so bump the pre cbmem console size
when building for Chrome OS so that all messages can be observed.
BUG=b:35775104
BRANCH=reef
TEST=Booted and noted no cutoff of console when sec data being saved.
Change-Id: I7a3bbe7a831538ce23010940dcfe38db8b23a8e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c7a477c5b
Original-Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18679
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452886
marshal_blob() was setting an unsigned size (size_t) to a value
of -1 when an error is determined. This is wrong for the current
implementation of the code because the code assumes the buffer
space gets set to 0. Setting an unsigned value to -1 effectively
tells the library the buffer has unlimited amount of space.
BUG=b:35775104
Change-Id: I0c823447bb771094a8fc5fce0fd0bb62fdcfcd14
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06f12f919f
Original-Change-Id: I677a1fd7528bef3ea7420d0a8d0a290e9b15cea3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18678
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452885
Fix the following error detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
TEST=Build and run on Galileo Gen2
Change-Id: I4df0f7f6d62561044605616aa623c2cfc2ccfa50
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 45fde705b6
Original-Change-Id: I8953fecbe75136ff989c9e3cf6c5e155dcee3c3b
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18698
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/452883
Fix the following warning detected by checkpatch.pl:
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: I134962a8312abd8fc10392768102585299ed6094
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f919ec476
Original-Change-Id: Ie4b41f6fb75142ddd75103a55e0347ed85e7e873
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18697
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452882
Fix the following errors detected by checkpatch.pl:
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: "foo * const * bar" should be "foo * const *bar"
TEST=Build and run on Galileo Gen2
Change-Id: I81197767b99948c51846217cb63400b5c3ea7da5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2d834a93a
Original-Change-Id: I0d20ca360d8829f7d7670bacf0da4a0300bfb0c1
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18696
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/452881
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
The remaining 37 warnings in gcov-io.c and libgcov.c are all false
positives generated by checkpatch detecting a symbol or function name
ending in _unsigned.
TEST=Build and run on Galileo Gen2
Change-Id: I746e85924f2f4684e3b67941fdfa3e5084c498f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75b859978a
Original-Change-Id: I9f1b71993caca8b3eb3f643525534a937d365ab3
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18695
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/452880
Fix the following error detected by checkpatch.pl:
ERROR: space prohibited after that '&' (ctx:ExW)
TEST=Build and run on Galileo Gen2
Change-Id: I2e92383212828c67c4ac71d0d11acd7e5e190ffc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18cb7e66bd
Original-Change-Id: Ied8b4c00fc57a35ed4d649264a5ff1b8dcc6a1cd
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18648
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452878
Fix the following error detected by checkpatch.pl:
ERROR: space required after that ',' (ctx:VxV)
TEST=Build and run on Galileo Gen2
Change-Id: I4025b28b4479350718da5403a2eb6c3dc9804fe9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae3fd34e00
Original-Change-Id: I297bfc3d03dc95b471d3bb4b13803e81963841b5
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18647
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452877
Fix the following error and warning detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
TEST=Build and run on Galileo Gen2
Change-Id: Ib4ccd723c74498beef266cc13ad428cfca7ddebd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 708fc274b5
Original-Change-Id: I487771b8f4d7e104457116b772cd32df5cd721a6
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18646
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452476
Fix the following error detected by checkpatch.py:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
False positives are generated when assembly code is used in a macro. An
example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $CONFIG_POST_IO_PORT
False positives are also generated for linker script include files. An
example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define SET_COUNTER(name, addr) \
+ _ = ASSERT(. <= addr, STR(name overlaps the previous region!));
\
+ . = addr;
False positives are also generated for attribute macros. An example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define DISABLE_TRACE_ON_FUNCTION __attribute__
((no_instrument_function));
TEST=Build and run on Galileo Gen2
Change-Id: Ie8ee87e4f64e1259d085ad562c7ea3e5c281a0a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb4ae07417
Original-Change-Id: I88abf96579e906f6962d558a3d09907f07d00b1c
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18644
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452475
Fix the following error detected by checkpatch.pl:
ERROR: trailing statements should be on next line
TEST=Build and run on Galileo Gen2
Change-Id: If0becceb9b15ff43fd2e5114fa71ab2c5b496c73
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0f5dfc678
Original-Change-Id: I169f520db6f62dfea50d2bb8fb69a8e8257f86c7
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18643
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452474
Fix warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2
Change-Id: If4e006aff16981e2e9b7ac38ea2909838b2660d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ca2a0654c
Original-Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18607
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452473
Add two GPIO macros:
1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
APIC with input assuming the events are edge triggered.
2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
input to SCI assuming the events are level triggered.
BUG=none
BRANCH=none
TEST=none
Change-Id: I38f8bb09537eaf41c89d584db767bda484181416
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75d8d8da47
Original-Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
Original-Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18533
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452472
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H
specifications to support sklrvp11.
Split the gpio_defs.h into headers gpio_pch_h_defs.h and
gpio_soc_defs.h for PCH-H specific and SOC specific GPIO
defs respectively.
BUG=none
BRANCH=none
TEST=none
Change-Id: I598225ee81d49b70965374bb888d3e3ad3c600bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a740539d1
Original-Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2
Original-Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com>
Original-Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18027
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452471
In all simplicity, with board/OptionsIds.h file having:
IDSOPT_IDS_ENABLED TRUE
IDSOPT_TRACING_ENABLED TRUE
And src/Kconfig modified to:
config WARNINGS_ARE_ERRORS
default n
With these settings AGESA outputs complete debugging log
where-ever you have your coreboot console configured.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id2a2b54b1aa2d2ad497b2fa25f418c52244c3fb3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86ee4db0d8
Original-Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15320
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452470
We have been forced to build AGESA with ASSERT() as non-fatal
for some board, as hitting those errors is not uncommon.
For the cases touched here, abort eventlog operations early
to avoid further errors and dereference of null pointers.
BUG=none
BRANCH=none
TEST=none
Change-Id: I342e3195585ca435749886e990b40ea65e2bd311
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bfa72ce23b
Original-Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18543
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452468
Implement threshold as described in AMD.h, and do not add
entries below STATUS_LOG_LEVEL in the eventlog.
BUG=none
BRANCH=none
TEST=none
Change-Id: I41a257d8482bdeb568689045511547484c33e3c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f74c89592
Original-Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18542
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452466
This is useful for debugging S3 issues and in general
to understand AGESA memory allocator behaviour.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6537ba637e2e7adbaf0f82481ff75cd4cfd110c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50e6daff95
Original-Change-Id: I422f2620ed0023f3920b8d2949ee1c33a6c227e0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18535
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452465
A problem around CAR teardown time may result with missing
training results at the time we want to save them.
Record this in the logs for debugging purposes, it will
not be possible to use S3 suspend if this happens.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1be67747db636b92ddc7c38d2d851ce81b7b359d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86690eb0a1
Original-Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18534
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/452464
When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.
Fixes regression with new toolchain using GCC-6.3 and
ec0a393 console: Enable printk for ENV_LIBAGESA
For some builds, the above-mentioned commit emitted
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5384281bdb98775fc6537734172c515eda58925a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 26929bd71a
Original-Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18622
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452463
The init files for the Core Duo and Core 2 Duo are very similar. Reduce
the differences, by using the same order for the include statements, the
same blank lines, and the same comments.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2ac2f5eda9f6d2dcc475d9363496dbcd26b9d03b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7129ccbd23
Original-Change-Id: I0de060222a61a482377c760c6031d73c7e318edf
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18506
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452461
This is required to transmit button information from EC to kernel.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I754490b80a191d298d748d21a3e8d5407a7895dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a89254801c
Original-Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18642
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452372
This is required to pass button information from EC to kernel without
using 8042 keyboard driver.
1. Define EC buttons device using GOOG0007 ACPI ID.
2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I30e42c66dec3a639c172df465a98e8bb9c03ebdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4a0a348e4
Original-Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18641
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452371
Apollolake platform comes with FPF (field-programmable-fuses). FPF can
be blown only once, typically at the end of the manufacturing process.
This patch adds code that sends a request to CSE to figure out if FPFs
have already been blown.
BUG=none
BRANCH=none
TEST=none
Change-Id: I45d74923d7b4dc8adb8bfa812965694abd75d5ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1aded2f0c
Original-Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18604
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452370
Add common driver that can send/receive HECI messages. This driver is
inspired by Linux kernel mei driver and somewhat based on Skylake's.
Currently it has been only tested on Apollolake.
BUG=b:35586975
BRANCH=reef
TEST=tested on Apollolake to send single messages and receive both
fragmented and non-fragmented versions.
Change-Id: Ia22e402e626e4da9dd75c934cbf0e142d1ec990e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 04a72c4019
Original-Change-Id: Ie3772700270f4f333292b80d59f79555851780f7
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18547
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452368
The __attribute__((weak)) lines on structs were being read as functions,
causing a warning that the brace should be on the next line.
Add a check to see if it's a struct with an attribute, and ignore it for
the OPEN_BRACE check if it is.
BUG=none
BRANCH=none
TEST=none
Change-Id: I69e9577374579bf24736b2961285938c124df8c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 010905ed2f
Original-Change-Id: Ieb0c96027e8df842f60ca7c9de7aac941eed1dc2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18570
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/452366
- Remove the "MISSING_SPACE" check which checks for breaks at a space in
a string concatenation. Most of the time this makes sense, but we
occasionally need to break where there isn't a space, so having a hard
rule doesn't always work.
- Don't check the vendorcode directory for compliance to coreboot's
code format rules.
BUG=none
BRANCH=none
TEST=none
Change-Id: If6648109dac8e91066f03e8d3c733db2f239b978
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e17eaed1b
Original-Change-Id: Ic07677b19520b5d22363834c77f5dee7bba9e429
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18569
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452365
