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UPSTREAM: cpu/intel/model_6{e,f}x: Unify init files

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The init files for the Core Duo and Core 2 Duo are very similar. Reduce
the differences, by using the same order for the include statements, the
same blank lines, and the same comments.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2ac2f5eda9f6d2dcc475d9363496dbcd26b9d03b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7129ccbd23
Original-Change-Id: I0de060222a61a482377c760c6031d73c7e318edf
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18506
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452461
This commit is contained in:
Paul Menzel 2017-02-27 01:01:55 +01:00 • committed by chrome-bot
commit 94e0c6ca37
2 changed files with 12 additions and 10 deletions
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11
src/cpu/intel/model_6ex/model_6ex_init.c
View file

@ -21,8 +21,8 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@ -34,10 +34,10 @@ static void configure_c_states(void)
msr_t msr;
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // config lock until next reset.
msr.lo |= (1 << 15); // config lock until next reset
msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo |= (1 << 3); //dynamic L2
msr.lo |= (1 << 3); // dynamic L2
/* Number of supported C-States */
msr.lo &= ~7;
@ -50,7 +50,7 @@ static void configure_c_states(void)
msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
wrmsr(MSR_PMG_IO_BASE_ADDR, msr);
/* set C_LVL controls */
/* Set C_LVL controls and IO Capture Address */
msr.hi = 0;
msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
@ -128,6 +128,9 @@ static void model_6ex_init(struct device *cpu)
x86_setup_mtrrs();
x86_mtrr_check();
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
/* Enable the local CPU APICs */
setup_lapic();

11
src/cpu/intel/model_6fx/model_6fx_init.c
View file

@ -21,9 +21,9 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/common/common.h>
@ -34,12 +34,11 @@ static void configure_c_states(void)
msr_t msr;
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // config lock until next reset
msr.lo |= (1 << 14); // Deeper Sleep
msr.lo |= (1 << 10); // Enable IO MWAIT redirection
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo |= (1 << 3); // Dynamic L2
msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo |= (1 << 3); // dynamic L2
/* Number of supported C-States */
msr.lo &= ~7;
@ -47,7 +46,7 @@ static void configure_c_states(void)
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE */
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;
msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
wrmsr(MSR_PMG_IO_BASE_ADDR, msr);