For adding missing \n, find all potential missings by below script
and apply manual checks and fixes.
grep -nE "(DEBUG|ERROR)\(\".+[^\\n]\"" util/cbfstool/ -r
For using __func__ in debug message, below script is used with
manual checks and fixes.
grep -nE "DEBUG\(.+:" util/cbfstool/ -r
Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86567
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace all occurrences of u8, u16, u32 and u64 with their respective
alternatives of uint8_t. There is no need to unnecessarily compress code
by using standard types aliases.
BUG=b:391874512
TEST=Compile cbmem
Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
We need to know how many combo entries have been processed.
It will be checked in functions in later change.
Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85590
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up the code to make it more logical.
This is for later changes to reorder the PSP Level 1, Level 2, ISH and
BIOS tables.
TEST=Identical test on all AMD platform
Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84531
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For A/B recovery, it is better, even though it is not mandatory, to
put BIOS level 2 table next to its PSP level2. So the relative
addresses of BIOS table are the same. So all the data in B could be a
copy of A.
Identical binary test on all non A/B recovery platform.
Booting test on Majolica with A/B recovery enabled.
Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the tooling necessary to build an Image that can be found and
started by ROM code of the JH7110 SOC.
source: https://github.com/starfive-tech/Tools
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iab16c1e1f15f24e85c0ef1a3e838d024e1e49286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83849
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Local tags (e.g. to keep track of builds) should not be used to describe
a board status report. This has happened in some cases, e.g. [1].
According to the Git 2.41.0 manual for git-describe, the '--tagged'
parameter is a way to also use any "lightweight (non-annotated) tag" in
addition to annotated tags, which are always used even without this
parameter. All coreboot release tags seem to be annotated, so this
option should be safe to drop.
[1] https://review.coreboot.org/plugins/gitiles/board-status/+/b8c47429bad5afc5cd7f798cad3dece9790a1f83
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I54b302415e569a3385559cc85323ce34462042ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79837
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The address field of each PSP or BIOS entry defines the location of
the entry.
For the family newer than Cezanne, the upper 2 bits define the address
mode. In table header, the address mode of the table is set. They have
the same definition.
Address Mode 0: Physical Address
Address Mode 1: Relative Address to entire BIOS image
Address Mode 2: Relative Address to PSP/BIOS directory
Address Mode 3: Relative Address to slot N
In common case, the address mode of entry should be the same as its
table. In spec, it says, "attribute is ignored if the directory
address mode is not 2 or 3",
In the old code, if the header defines address mode as relative BIOS(1),
the entry address mode is not set. That meets the spec. PSP doesn't
use, but amdfwtool can use it to record the address mode and transfer
it to table. That can reduce the code complexity.
Identidal binary test passes on platforms which are not based on
Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne.
Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84530
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit adds a new event type, `ELOG_TYPE_LOW_BATTERY_INDICATOR`,
to the event log. This event is logged when the system boots due to
a low battery condition. It includes the reason for the shutdown,
currently only supporting "Power Off".
BUG=b:339673254
TEST=Able to capture the eventlog for low battery boot event.
```
> elogtool list
9 | 2025-02-03 09:44:19+0530 | Low Battery Boot | Power Off
```
Change-Id: I5cc5e5f540657c7dfd174a4928e697a272da813a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpEnable[] is a boolean, so use true false instead of 0 1.
Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
All of the other targets support invoking the build with the full target
arch name. RISC does not. Update the script to allow riscv64-elf to
invoke the build the same way that riscv-elf does to minimize name
mangling and exceptions needed for tooling surrounding the
architecture name in paths. Leave riscv-elf in tact as an option so
we don't break anyone else.
BUG=None
TEST=./util/crossgcc/buildgcc --platform riscv64-elf
Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the printing of the missing libstdcxx path in the warning string
when the path check fails. Also resolve the use of the variable in
the conditional statement by surrounding it with quotes.
BUG=None
TEST=Build with invalid libstdcxx path
Change-Id: I195718e43ea842970f5fa986315c9e9f11395362
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86148
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some newer boards (like google/skyrim) use a separate line for each
field, so adjust parsing to accommodate that.
TEST=run `bash crosfirmware.sh` for frostflow, grunt, careena.
Change-Id: I3af38d3577f1390c999ad5e6df0fa2c4c4382245
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Also add an interface for printing macros to override this in the test
and not create a new gpio file for comparison.
Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67701
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the aliases are used and already contain the device name,
there's reason to generate these in the first place.
TEST=Ran autoport with logs from ASRock Z77 Extreme4.
Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85822
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since add-int is intended for manipulating options stored as integers in
CBFS (such as SeaBIOS runtime config options), removing the file so that
it can be re-added with a new value is a common action. Attempt to
remove the existing integer automatically if it already exists to remove
the need for the extra step.
Change-Id: I5a0ac409fc9b91a4f7c0c35650875d6211ac2b25
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86009
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To ensure we find the correct firmware image, match against `$BOARD":`
rather than just `$BOARD`. This fixes an issue where another board (b1)
using the same firmware build or name as the one we are searching for,
causes the grep matching to return empty strings.
TEST=successfully extract the firmware image for CAREENA, which
previously failed.
Change-Id: I2f2a71f0b033938aafc1fd27e2996fe319614b3c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit e24294ff9ade ("lsusb -t: print ports and busses and devices with
same width") [1] in the usbutils repository changed the format of the
lsusb -t output, breaking the find_usbdebug.sh script. This commit is
present in usbutils version 016 and later.
Use the output of lsusb -V to set the parsing patterns based on the
version in order to maintain compatibility with older versions of
usbutils. A simple integer comparison of the version number is used for
this, which will not work with versions older than v001 as those use a
0.nn version number format. However, since v001 was released in late
2010, it is probably safe to assume that no one will be using a version
of usbutils older than that. Usbutils v016 was released in late 2023 so
there could still conceivably be systems using older versions, such as
Ubuntu 22.04 LTS which is on v014.
TEST=find_usbdebug.sh works as expected with both lsusb v015 and v017
[1] e24294ff9a
Change-Id: Iffa1238b995d387d6e51459f85ae96da52a5c0ff
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85790
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since Python 3.12, invalid escape sequences produce a SyntaxWarning;
in the future, they will produce SyntaxError.
Using raw strings clear out the warning.
Below the command used for checking the fix worked.
```
$ python3 util/lint/checkpatch_json.py
```
Link: https://docs.python.org/3.12/whatsnew/3.12.html#other-language-changes
Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7
Signed-off-by: Ariel Otilibili <otilibil@eurecom.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85771
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add a check to make sure lsusb and lspci are installed, as the script
relies on them to function properly. Previously, if lsusb was not
installed, the script proceeded as if nothing was wrong, but never found
any devices plugged into the debug port. If lspci was not found, the
script exited saying that no EHCI debug capable controller was found.
The "command not found" messages that normally would have been shown in
these situations was not being shown, as stderr is redirected to
/dev/null to hide error messages that don't matter as per the comment
near the top of the script.
Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
As suggested by the linter:
> Prefer 'unsigned long' over 'unsigned long int' as the int is
> unnecessary
In fmap_bsearch(), removed needless assignment of offset; it is already
set to 0 in the search loop.
fmap_find() uses the return value of fmap_bsearch(); and is declared as
'long int'. Per the linter warnings, replaced 'long int' by 'long'.
> Prefer 'long' over 'long int' as the int is unnecessary
Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
Change-Id: If94e70778d0302552f151c31d3073524162faf9e
Signed-off-by: Ariel Otilibili <otilibil@eurecom.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85786
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The layout of an extracted REEF shellball doesn't conform to the
usual ones used by other boards, so add a special-case handler for it.
TEST= run `bash croshfirmware.sh reef` and receive the correct firmware
image for the board.
Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85873
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since commit 34a7e66faa ("util/cbfstool: Add a new mechanism to
provide a memory map") the ext-win-base and ext-win-size option has been
replaced with the "--mmap" option.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I33cfb59d9dbe88c4f618301ac1506e3281b1a483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
has_power_resource is a boolean, so use true, false instead of 0, 1.
Change-Id: I25b86ef577e072cfe3ef5dc2447113f11c51f747
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch enhances the readability of the CSE sync event
ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late
bootstage" to "pre and post memory."
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
without change:
```
rex-rev3 ~ # elogtool list
rex64-rev3 ~ # /media/usb/elogtool list
3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync
```
with change:
```
rex64-rev3 ~ # elogtool list
3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync
```
Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Depending on the environment, the /data-in directory might be owned by
root and recent git versions refuse to work in these. So explicitly
mark /data-in as a safe environment.
Change-Id: Ia534928f759e50c2dfb1df8af653dee74c734603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
There is no reason to stick to the point releases. So use the 3.19 base
image referring to the latest minor release instead. Also, update
installed packages to latest versions from that release.
Change-Id: Ic947f99ae7231918ec2e6105f8f3050a17fd1176
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
It seems the .bashrc is not loaded as intended and thus the bash
mechanisms never worked. So drop the bash invocations and replace them
with the ash shell. Also, don't modify the PATH variable since this is
done by the activation script.
Change-Id: I544a15c86c212e91ece59b583fb61dad37fca337
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Volumes are mounted with the command line parameter. Using the VOLUME
directive creates a persistent storage in a standard path, which is not
intended. So drop that and create equal directories in order to keep the
container working.
Change-Id: I9b3551cca34d846aba5ca5c89162f82baa6de768
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85724
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This to upgrade iasl from 20230628 to 20241212.
Change-Id: I4ae7073e46084024360ac0dd44e0df666cb32269
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This allows building coreboot with AddressSanitizer on ChromeOS.
Otherwise these memory leaks are detected which cause the build to fail.
Change-Id: Ife6114db99278c9a3fb8271410486b057ef822f6
Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add target for building libstdcxx for a cross compile target using the
GCC source downloaded for a cross compiler build and linking against a
specified libc implementation.
BUG=NONE
TEST=Build libstdc++ for cross compilers, link against generated library
./util/crossgcc/buildgcc -t -p arm-eabi -P libstdcxx -l c,c++ -j128 \
--libstdcxx_include /tmp/picolibc
Change-Id: Ie0c06ffaeab632c27a992dee8abcc403cceabeed
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
