As we now apply asmlinkage attributes to romstage_main()
entry, also x86_64 passes parameters on the stack.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idc959f24a256aa5c77b00b030b2d01b0ea6dd127
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: df7ff31c59
Original-Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18624
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471448
Function enables PCI MMCONF and XIP cache, it needs
to be called before giving platform any chance of
calling any PCI access functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib1e1131ad5e149a81da19bb6cdb2945450ea9b60
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 13cf135871
Original-Change-Id: Ic044d4df7b93667fa987c29c810d0bd826af87ad
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18623
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471447
pci_lookup_name might return NULL from using format_name internally
which could cause a crash when trying to print that value. We
check for NULL and print a more appropriate value in that case.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4dcf7aafb583473e1e6e5a9d2a3192743678fcb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b85ddc787e
Original-Change-Id: I499f0b5e1681f3926df0d8a325aab2c666ebd632
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19089
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/468733
Add 100 Mhz reflock default values for Ivybridge.
Some values are extracted from MRC, those marked as
guessed needs to be verified.
Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idf1d41e32a767fe7d250942834da69a2e2aecb1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb7d6a19bb
Original-Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17609
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/468732
BUG=b:35583511
BRANCH=gru
TEST=check i2c bus 0 initializes from ap console log
Change-Id: Ib45f90313852601e6a4f9e23b36bc6f46bb3f4d6
Signed-off-by: Philip Chen <philipchen@google.com>
Original-change-Id: Ibb6709159f5ed28ad0b62397d2ddb504dec55167
Original-signed-off-by: Philip Chen <philipchen@google.com>
Original-reviewed-on: https://review.coreboot.org/19105
Original-tested-by: build bot (Jenkins)
Original-reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/470566
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add support for 100MHz reference clock on ivybridge.
Allows to use more frequencies than sandybridge.
Tested on Lenovo T430 (Intel IvyBridge) on DDR3-1800.
BUG=none
BRANCH=none
TEST=none
Change-Id: I229d37937faff78ffa20a85e21f132d9008d26d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cab4d3df39
Original-Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17607
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/468730
Use Ivy Bridge specific magic values on Ivy Bridge instead
of Sandy Bridge values.
The values are extracted from MRC.bin.
Should increase raminit stability.
Tested on Lenovo T430 (Intel IvyBridge).
BUG=none
BRANCH=none
TEST=none
Change-Id: I900ed32dcb116d359c41e64fd096ffc814587926
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77eaba3618
Original-Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17606
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/468729
- Add --checksum command line parameter to specify a base path and
filename for the checksums to be saved into.
- Save checksums of each platform into the specified file appended
with "_platform"
- Save a sha256 checksum of the sorted config.h into the base file
appended with "_config"
BUG=none
BRANCH=none
TEST=none
Change-Id: I39327acf173a5de49b828272e4f7ff8d8c303217
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7e6ad7be2
Original-Change-Id: Id24dc4b10afbd35cdb8750f75b934419e6e80290
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19033
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/468727
- Remove document history. Since the document is now stored in git,
this is no longer needed.
- Fix spacing for the kconfig_lint help output
- Add license information to the bottom of the document.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1fb84911b132df03a5d6177dafa7d7f92939c749
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0090192ddd
Original-Change-Id: I9854602a6ad9b4a99bf3988e1d7662b3b426e608
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19075
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/468726
This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC
provides a display controller with three independent pipes (1x eDP and
2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device
that enables connectivity between an eDP source and LVDS display panel
(http://www.nxp.com/documents/data_sheet/PTN3460.pdf).
The bridge contains an On-chip Extended Display Identification Data
(EDIT) emulation for EDIT data structures.
This patch sets up PTN3460 to be used with the appropriate LCD panel.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1b69b1411786343417bc49b43a1300315c0fe252
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 956a9f6a9c
Original-Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19043
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/467112
This was guarded because AGESA.h only defined it starting from fam15
header files. We can simply test if it has been defined.
The way coreboot currently handles this request, is to make the
allocation outside the heap, since heap may not be in CBMEM and thus
not available runtime. The acquired buffer from Allocate() would not
be found with Locate() or Deallocate(), so move the alloc_cbmem()
call for better code symmetry.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id9ce566cd144da8ebf470ace7df2cfb90ebca12d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bceccec0f7
Original-Change-Id: Ibf0066913a0b73e768488c3afbeb70139a3961eb
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19039
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/467110
Once we do CAR teardown between AmdInitResume() and
AmdS3LateRestore() we attempt to find our heap from the
temporary memory buffer instead of cache.
S3 resume is essentially broken anyways and this is not yet a
proper fix at all, but barely keeps system from halting on S3
resume.
Offset that seems arbitrary was taken from hudson/agesawrapper.c.
BUG=none
BRANCH=none
TEST=none
Change-Id: I26ac7d9b1f5bf27871faf32e02bacc1d21c9ebc1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42402772e5
Original-Change-Id: Idddf2ecde5a9d32d532071d6ba05032be730460c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19038
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/467109
Producer and consumer of these buffers now appear in same file.
Also add test for uninitialized NonVolatileStorage in SPI.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2af72fb451ee9faa5efa14fcbcaf8083a85f7b69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 424c63950b
Original-Change-Id: Ibbf6581a0bf1d4bffda870fc055721627b538b92
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19037
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/467108
- Add some variables to allow server customizations.
- Verify that coreboot images and containers exist before trying to
remove them.
- Add a couple of convenience targets: clean & cleanall to remove
coreboot containers and images or ALL containers and images.
- Add docker-what-jenkins-does target to run a test build locally inside
a docker image.
- Add docker-jenkins-server target to test the server configuration and
run the jenkins docker image.
- Add docker-jenkins-shell and docker-shell targets to run the
coreboot-sdk and coreboot-jenkins-server images.
- Update the help.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idcb7fcf7812283294e142bb94347aa0bc525a112
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 85782b2152
Original-Change-Id: I1896f33e7eddfe3248f44ae780de65ce50d5dd99
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18004
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/467107
pci_me_interface_scan was returning (via argument 'name') a pointer
to the interface name which was stored in a stack variable. This
caused part of the name to be printed as garbage stack data in some
situations if stack data was overwritten.
This moves the name buffer to the calling function so it can be accessed
before it gets overwritten.
BUG=none
BRANCH=none
TEST=none
Change-Id: If90d643cac4ab73e0c7910c12b8bc4694e872664
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0c53af470
Original-Change-Id: I947a4c794ee37fe87e035593eaabcaf963b9875e
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19066
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/467106
Only guard the parts that are problematic for romstage.
Also intention is to move AMD_S3LATE_RESTORE to ramstage in followup
work, it will need OemS3LateRestore.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idc337f6edd1d4647037fac177b8d0e85610e6596
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d5321c9c4
Original-Change-Id: Ie9c1fb3f3f0ab1951771ed829d4acdd8a59d8fbf
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19025
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466060
Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so the buffer is not invalidated without writeback.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib17675c8cddb8b1266f389b6a2c505713897da64
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a6e00fd36
Original-Change-Id: I3a5d497d0e25ec291f722e9f089bc8928238c3f9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19024
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466059
Logging makes it easier to track order of events as these
call-sites are scattered on various files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5392a0b83fb08c1f8797b3a8ea459fdb0d60bb7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1498efe2d0
Original-Change-Id: I428547051fd8bf487e91415dc72ee03dba13029e
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18718
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466058
The tis.c module is needlessly copying data to/from a 1260 byte
buffer on the stack. Each device's transport implementation (cr50.c
or tpm.c) maintains its own buffer, if needed, for framing purposes.
Therefore, remove the duplicated buffer.
BUG=b:36598499
Change-Id: I091309f0fd45943b974d5244ae79c01eed618f16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92190198b0
Original-Change-Id: I478fb57cb65509b5d74bdd871f1a231f8080bc2f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19061
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/466056
The spi tis_sendrecv() implementation was always returning success
for all transactions. Correct this by returning -1 on error when
tpm2_process_command() returns 0 since that's its current failure
return code.
BUG=b:36598499
Change-Id: I614d05e76f8f09e071405b1acdc68db6ab989976
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ef52cd751
Original-Change-Id: I8bfb5a09198ae4c293330e770271773a185d5061
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19058
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/466053
The tpm_info object is a global, but its symbol does not need to
be exposed to the world as its only used within tpm.c.
BUG=b:36598499
Change-Id: I10d2d75641ed3ce9d3fda27c382348c9c90542aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 445c13fb5d
Original-Change-Id: Idded3dad8d0d1c3535bddfb359009210d3439703
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19057
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/466052
In the case of start_transaction() failing the chip select is never
deasserted. Correct that by deasserting the chip select when
start_transaction() fails.
BUG=b:36598499
Change-Id: I91866a30fca8c9efae15a900722eb0fc3bebbfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5cf1fadeca
Original-Change-Id: I2c5200085eb357259edab39c1a0fa7b1d81ba7b2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19056
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466051
Currently only 256 bytes can be written at a time using the
acpigen_write_return_byte_buffer or acpigen_write_byte_buffer API's
and there can be cases where the buffer size can exceed this, hence
increase the number of bytes that can be written.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1e7db59aca3bde85eb1f171a7e95854c1f438bcb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aca4c94057
Original-Change-Id: Ifaf508ae1d5c0eb2629ca112224bfeae1c644e58
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18966
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/466049
With COREBOOT_BUILD_DIR set, nvramcui & coreinfo were getting built
in the wrong location, causing those builds to fail.
Also, because they were built in the wrong location, the build failures
were not detected by jenkins which was looking for the junit.xml files
under the payloads directory.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iccb30a12aeebb1839ab265935b3332d6ed2f5fc1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee762fa42b
Original-Change-Id: I9d81ebabebe5d8b5f79ae63f8a5f388430e06754
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19069
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/466048
There's a missing closing brace in fillbits function of jpeg.c which
caused an avalanche of compilation errors.
This was introduced in commit
491c5b60 (src/lib: Move assignment out of if condition)
which was reviewed in gerrit at https://review.coreboot.org/18761 and it
prevents coreboot from building when CONFIG_BOOTSPLASH is set.
BUG=none
BRANCH=none
TEST=none
Change-Id: I60eb0319dd3ae170694ba8e0b570876f646d917c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d24dbf9902
Original-Change-Id: Ie10b774875fc25ce2ff613c542c15870e780a761
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19032
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/462963
Wake On Voice stream capture configuration is mono. It is sufficient
to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1.
Power saving should be visible in the boards which has more
than one DMIC connected.
BUG=None
BRANCH=None
TEST=WoV and quad channel DMIC capture works
Change-Id: Ide41768001b535141948d6d0290725ae29a744ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e2370075d
Original-Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03
Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19018
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/462959
Use the new parameters in amdfwtool to include the additional SMU
firmware into amdfw.rom.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ief97b0f10459dbdfb623f36fc5840f8662347c6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0cd2cb6cae
Original-Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19002
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462957
Change the current implementation so that multiple PSP directory
structures are not included, saving 448 KB.
AMD created a mechanism so that multiple generations of APUs, in
identical packages, may be supportable in one BIOS image. The PSP
identifies the correct directory table by checking one of two
pointers in the Embedded Firmware structure. Coreboot doesn't
implement this capability, however it has been constructing
amdfw.rom with two identical directory tables and two copies of
each PSP blob.
Tested on Bettong (Merlin Falcon / Carrizo) and Jadeite (Stoney).
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 11dfc3f621344db66d92b61d72927128ea48685f)
BUG=none
BRANCH=none
TEST=none
Change-Id: I05e17055775d02fdd61a5dfd06e6d08742219281
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7fd0bc84ff
Original-Change-Id: I139f3bfdb319af803fef64e7bd848e95945f41aa
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18990
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462956
For systems using Chrome OS, place the amdfw outside of cbfs control.
The firmware must go to a fixed position at an offset of 0x20000 into
the flash device.
Potentially improve by adding a warning or error message for the
condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash).
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1)
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f98ea97aaf8fc3a08ebc907ea0cb7a3cbc73aa3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c6be0d854a
Original-Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18435
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462955
The Stoney Ridge program has OPNs that are considered fanless. These
APUs are strapped to search for unique SMU firmware, indicated by
Type[8]=1 in the directory table entry.
Add new options to amdfwtool and include the blobs in the build with
the appropriate bit set in the Type encoding.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da)
BUG=none
BRANCH=none
TEST=none
Change-Id: I0366e548ab618a2200403b1262451727c095916c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4b9b41c47
Original-Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18991
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462954
This patch currently contains the SA initialization
required for bootblock phase -
1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I73657150cda113d27ccac3952d5ec05cd642e5fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7952e283fb
Original-Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18567
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/462953
This patch currently contains the SA initialization
required for bootblock phase -
1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id56ece7a40ce573846a642c4b08d37fcadc75107
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93ebe499d4
Original-Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18566
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462952
Create common Intel systemagent code.
This code currently contains the SA initialization
required in Bootblock phase, which has the following programming-
* Set PCIEXBAR
* Clear TSEG register
More code will get added up in the subsequent phases.
BUG=none
BRANCH=none
TEST=none
Change-Id: I246bc9298a0bc25304ee57e909ffa8993b7e0074
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01ae11b057
Original-Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18565
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462951
This patch to make common PCI device name between APL and SKL.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic74d1c1708285500210be34c3c2b71c4b90404f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ee54db246
Original-Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18576
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462950
This patch currently contains common CAR initialization
required in bootblock phase along with common MSR header -
1. Use SOC_INTEL_COMMON_BLOCK_CAR to have common CAR initialization
and CAR teardown.
2. Use common MSR header "intelblocks/msr.h" inside soc/cpu.h
BUG=none
BRANCH=none
TEST=none
Change-Id: I24e83349bc89c2793f1a3376fdf7796d7d641800
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc4c7d8320
Original-Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18555
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462949
