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UPSTREAM: nb/intel/sandybridge/raminit: Add default values

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Add 100 Mhz reflock default values for Ivybridge.
Some values are extracted from MRC, those marked as
guessed needs to be verified.

Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800.

BUG=none
BRANCH=none
TEST=none

Change-Id: Idf1d41e32a767fe7d250942834da69a2e2aecb1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb7d6a19bb
Original-Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17609
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/468732
This commit is contained in:
Patrick Rudolph 2016-11-25 15:40:49 +01:00 • committed by chrome-bot
commit 60ec2ddeeb
1 changed files with 48 additions and 3 deletions
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51
src/northbridge/intel/sandybridge/raminit_ivy.c
View file

@ -292,10 +292,28 @@ static void dram_timing(ramctr_timing * ctrl)
u8 val;
u32 val32;
/* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure
* we cap it if we have faster DIMMs.
/* Maximum supported DDR3 frequency is 1400MHz (DDR3 2800).
* We cap it at 1200Mhz (DDR3 2400).
* Then, align it to the closest JEDEC standard frequency */
if (ctrl->tCK <= TCK_1066MHZ) {
if (ctrl->tCK <= TCK_1200MHZ) {
ctrl->tCK = TCK_1200MHZ;
ctrl->edge_offset[0] = 18; //XXX: guessed
ctrl->edge_offset[1] = 8;
ctrl->edge_offset[2] = 8;
ctrl->timC_offset[0] = 20; //XXX: guessed
ctrl->timC_offset[1] = 8;
ctrl->timC_offset[2] = 8;
ctrl->reg_320c_range_threshold = 10;
} else if (ctrl->tCK <= TCK_1100MHZ) {
ctrl->tCK = TCK_1100MHZ;
ctrl->edge_offset[0] = 17; //XXX: guessed
ctrl->edge_offset[1] = 7;
ctrl->edge_offset[2] = 7;
ctrl->timC_offset[0] = 19; //XXX: guessed
ctrl->timC_offset[1] = 7;
ctrl->timC_offset[2] = 7;
ctrl->reg_320c_range_threshold = 13;
} else if (ctrl->tCK <= TCK_1066MHZ) {
ctrl->tCK = TCK_1066MHZ;
ctrl->edge_offset[0] = 16;
ctrl->edge_offset[1] = 7;
@ -304,6 +322,15 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[1] = 7;
ctrl->timC_offset[2] = 7;
ctrl->reg_320c_range_threshold = 13;
} else if (ctrl->tCK <= TCK_1000MHZ) {
ctrl->tCK = TCK_1000MHZ;
ctrl->edge_offset[0] = 15; //XXX: guessed
ctrl->edge_offset[1] = 6;
ctrl->edge_offset[2] = 6;
ctrl->timC_offset[0] = 17; //XXX: guessed
ctrl->timC_offset[1] = 6;
ctrl->timC_offset[2] = 6;
ctrl->reg_320c_range_threshold = 13;
} else if (ctrl->tCK <= TCK_933MHZ) {
ctrl->tCK = TCK_933MHZ;
ctrl->edge_offset[0] = 14;
@ -313,6 +340,15 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[1] = 6;
ctrl->timC_offset[2] = 6;
ctrl->reg_320c_range_threshold = 15;
} else if (ctrl->tCK <= TCK_900MHZ) {
ctrl->tCK = TCK_900MHZ;
ctrl->edge_offset[0] = 14; //XXX: guessed
ctrl->edge_offset[1] = 6;
ctrl->edge_offset[2] = 6;
ctrl->timC_offset[0] = 15; //XXX: guessed
ctrl->timC_offset[1] = 6;
ctrl->timC_offset[2] = 6;
ctrl->reg_320c_range_threshold = 12;
} else if (ctrl->tCK <= TCK_800MHZ) {
ctrl->tCK = TCK_800MHZ;
ctrl->edge_offset[0] = 13;
@ -322,6 +358,15 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[1] = 5;
ctrl->timC_offset[2] = 5;
ctrl->reg_320c_range_threshold = 15;
} else if (ctrl->tCK <= TCK_700MHZ) {
ctrl->tCK = TCK_700MHZ;
ctrl->edge_offset[0] = 13; //XXX: guessed
ctrl->edge_offset[1] = 5;
ctrl->edge_offset[2] = 5;
ctrl->timC_offset[0] = 14; //XXX: guessed
ctrl->timC_offset[1] = 5;
ctrl->timC_offset[2] = 5;
ctrl->reg_320c_range_threshold = 16;
} else if (ctrl->tCK <= TCK_666MHZ) {
ctrl->tCK = TCK_666MHZ;
ctrl->edge_offset[0] = 10;