UPSTREAM: AGESA: Move amd_initmmio() call

Function enables PCI MMCONF and XIP cache, it needs
to be called before giving platform any chance of
calling any PCI access functions.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ib1e1131ad5e149a81da19bb6cdb2945450ea9b60
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 13cf135871
Original-Change-Id: Ic044d4df7b93667fa987c29c810d0bd826af87ad
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18623
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471447

src/cpu/amd/agesa/cache_as_ram.inc

@@ -108,19 +108,24 @@ cache_as_ram_setup:
   # use call far to switch to 64-bit code segment
   ljmp $0x18, $1f
 1:
+
+  .code64
+
+  call early_all_cores
+
   /* Pass the cpu_init_detected */
   cvtsd2si        %xmm1, %esi
 
   /* Pass the BIST result */
   cvtsd2si        %xmm0, %edi
 
-
-  .code64
   call    cache_as_ram_main
   .code32
 
 #else
 
+  call early_all_cores
+
   /* Restore the BIST result */
   cvtsd2si  %xmm0, %edx
 

src/cpu/amd/agesa/family12/romstage.c

@@ -35,13 +35,17 @@
 #include <arch/cpu.h>
 #include "platform_cfg.h"
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
 	post_code(0x35);
-	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);

src/cpu/amd/agesa/family14/romstage.c

@@ -39,13 +39,16 @@
 #include <cpu/amd/car.h>
 #include <sb_cimx.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		sb_Poweron_Init();

src/cpu/amd/agesa/family15/romstage.c

@@ -30,13 +30,16 @@
 #include <nb_cimx.h>
 #include <sb_cimx.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	post_code(0x30);
-	amd_initmmio();
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */

src/cpu/amd/agesa/family15rl/romstage.c

@@ -33,13 +33,16 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		board_BeforeAgesa(cb);

src/cpu/amd/agesa/family15tn/romstage.c

@@ -34,13 +34,16 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/cpu/amd/agesa/family16kb/romstage.c

@@ -33,13 +33,16 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/include/cpu/amd/car.h

@@ -16,4 +16,6 @@ void cache_as_ram_new_stack(void);
 void disable_cache_as_ram(void);
 #endif
 
+void asmlinkage early_all_cores(void);
+
 #endif