Read-only mirror of https://review.coreboot.org/coreboot.git. Synced every hour. We don't handle Pull Requests. https://coreboot.org
  • C 93.8%
  • ASL 2.2%
  • Makefile 1.1%
  • C++ 0.5%
  • Pawn 0.5%
  • Other 1.8%
Find a file
Marshall Dawson 38b0d5a565 UPSTREAM: amd/pi/hudson: Reduce amdfw space requirement
Change the current implementation so that multiple PSP directory
structures are not included, saving 448 KB.

AMD created a mechanism so that multiple generations of APUs, in
identical packages, may be supportable in one BIOS image.  The PSP
identifies the correct directory table by checking one of two
pointers in the Embedded Firmware structure.  Coreboot doesn't
implement this capability, however it has been constructing
amdfw.rom with two identical directory tables and two copies of
each PSP blob.

Tested on Bettong (Merlin Falcon / Carrizo) and Jadeite (Stoney).

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 11dfc3f621344db66d92b61d72927128ea48685f)

BUG=none
BRANCH=none
TEST=none

Change-Id: I05e17055775d02fdd61a5dfd06e6d08742219281
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7fd0bc84ff
Original-Change-Id: I139f3bfdb319af803fef64e7bd848e95945f41aa
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18990
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462956
2017-03-30 05:30:06 -07:00
configs UPSTREAM: configs/builder: Remove pre-defined VGA bios file 2017-01-22 05:03:18 -08:00
Documentation UPSTREAM: Documentation: Add doxygen_platform target 2017-03-25 10:22:57 -07:00
payloads UPSTREAM: tint: Add USB support 2017-03-20 17:33:14 -07:00
src UPSTREAM: amd/pi/hudson: Reduce amdfw space requirement 2017-03-30 05:30:06 -07:00
util UPSTREAM: util/amdfwtool: Add fanless SMU firmware options 2017-03-30 05:30:05 -07:00
.checkpatch.conf Drop --exclude statement from .checkpatch.conf 2017-03-13 17:53:59 -07:00
.clang-format
.gitignore UPSTREAM: .gitignore: ignore *.swo and option *.roms 2017-03-10 10:54:46 -08:00
.gitmodules Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
.gitreview
COMMIT-QUEUE.ini DO NOT UPSTREAM: COMMIT-QUEUE: Configure pre-CQ for more coverage 2017-03-29 13:43:13 -07:00
COPYING
gnat.adc UPSTREAM: gnat.adc: Do not generate assertion code for Refined_Post 2016-11-03 14:44:05 -07:00
MAINTAINERS UPSTREAM: MAINTAINERS: Update list 2017-03-08 05:13:03 -08:00
Makefile UPSTREAM: Remove libverstage as separate library and source file class 2017-03-29 13:43:09 -07:00
Makefile.inc UPSTREAM: Remove libverstage as separate library and source file class 2017-03-29 13:43:09 -07:00
PRESUBMIT.cfg Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
README UPSTREAM: Remove extra newlines from the end of all coreboot files. 2016-08-04 23:36:56 -07:00
toolchain.inc UPSTREAM: Remove libverstage as separate library and source file class 2017-03-29 13:43:09 -07:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.