Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216426
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to enumerate CPU devices that are non-x86 (read: no lapic)
provide a generic 'cpu' device.
Upstream patch: http://review.coreboot.org/#/c/6824/
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built a device tree with 'cpu' entries.
Change-Id: Ic3aa09970e5dd3d175048d698f74e2cce790dff0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216424
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31812
TEST=check if TS is found by the kernel
Change-Id: I22e6a9b65253bd17b639ce4d0742d1e7d3109e0c
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216527
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Instead of directly using the clk_src_id based on enum for clock source, every
device needs to have its own set of clk source ids defined. This prevents from
accidentally selecting a wrong clk source if the ids are changed as for host1x.
Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id
represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for
handling the common clock sources based on id to get the proper frequency in
software.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216761
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Provide access to the MIDR_EL1 register to obtain the
main id for determining CPU implementer and part/revision
information.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and printed the output of this function on ryu.
Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216423
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The host1x clock selection register has a different encoding
than the major of other clock source registers. This results
in PLLM_OUT0 being selected when PLLP_OUT0 was requested.
Use the clock_configure_irregular_source() method to correct
this situation.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Noted proper clock selection was achieved.
Change-Id: Idc1ea88e2e1f2abc0c13e7aa1e8bdfa981da388e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216422
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
This function is breaking display bring up in the kernel. While
this functionality may be needed it's not until there is a
necessity to beep and/or bring up the display in firmware.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Sean ran with this patch and the display indeed did come up.
Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216421
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The VBIOS DID and the id in config file are inconsistent.
Without this commint, you will need to skip error during
suspend stress test
BUG=chrome-os-partner:31286
BRANCH=none
TEST=build ok, check no ERROR exists in log
Change-Id: Ia73cb4cc4f4b0844a0692f6e760bcc089d64d09c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/216172
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
BUG=chrome-os-partner:29778
TEST=emerge-veyron libpayload
Change-Id: Idad1ad165fd44df635a0cb13bfec6fada1378bc8
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/211053
Reviewed-by: Julius Werner <jwerner@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209469
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
There is no proto function for mainboard_suspend_resume
In this case mainboard_suspend_resume is not NULL,
and cause if statment true.
Bios will jump to an empty weak function,
if mainboard_suspend_resume is not defined in mainboard.c
Then system becomes panic during s3 resume
BUG=chrome-os-partner:31286
TEST=compile ok and make sure system can resume from s3
BRANCH=None
Change-Id: I76bdea1d96166e683c6284024e1befbfc0d64645
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/215865
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Removing BOOTROM_SDRAM_INIT from Ryu's config
allows the code in sdram.c to handle LPDDR3 init
for all 3 SDRAM vendors now.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BUILD=None
TEST=Built for rush and rush_ryu, booted Ryu to kernel
login AOK (w/Samsung LPDDR3). Booted Rush to where it
tried to load in the Ryu kernel (need to create Rush
boot media). Micron and Hynix SDRAM boards need test
(none here in AZ).
Change-Id: Ieaa880f955e546e707230ba34e09594410c5fd8a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/215864
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are used by the LPDDR3 code in sdram.c.
Based on the schematic and email, I've filled in 4 slots
in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits
1:0) for Samsung SDRAM. I haven't tested the other 2 types of
RAM (Hynix and Micron). The 4th slot is a fallback slow Micron
config.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/216000
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are not needed/were never really used. SDRAM init will now
be done in sdram.c, not the BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built rush_ryu AOK.
Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/215863
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Expanded sdram.c to add support for LPDDR3 init. This code can
be used with matching BCT .inc files to have LPDDR3 SDRAM
initialized by coreboot instead of the T132 BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/214753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This allows to build coreboot for the mips based board called urara.
BUG=chrome-os-partner:31438
TEST=emerge-urara coreboot succeeds with the proper coreboot image
created. No testing yet.
Change-Id: I420476802fb12e5d02f07998d6c01d8c38b7a83e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not much is happening yet, when the board is enabled (in the next
patch), all three components build successfully, the map files show
them placed where expected and the bopotblock is wrappeed in a BIMG
header.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214600
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Romstage initialization code does not need to be board specific, keep
it in the SOC directory. Should there be a need for the board specific
code, it can be added later.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215992
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the proper configuration flags enabled, do_printk is available
from src/console, no need to define it elsewhere.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When doing an EC requested reboot to RO mode clear the
saved post code in order to prevent confusing events in
the log where the system is rebooted intentionally.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus, run FAFT, check for odd
eventlog entries about last post code 0x31 when it is
rebooted during samus romstage entry point.
Change-Id: I8bedc611712424bf1044cdca1972e34ffdd51abd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215681
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These modules are necessary to resolve external names when building
the board image. These are just skeletons for now which will be filled
later.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215678
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The upcoming MIPS toolchain inside chroot generates elf images of
elf32-tradlittlemips format, whereas readily available tools outside
of chroot generate images of elf32-littlemips format. Both of these
formats are perfectly fine, but xcompile accepts only one format per
CPU architecture.
This patch allows to specify multiple formats per architecture, any
matching format will suffice.
BUG=chrome-os-partner:31438
TEST=emerged arm, x86 and mips targets inside chroot
Change-Id: I22405e71ac72b985fad51e2f5d7cc014107b8a9e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214599
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MIPS targets should be compiled with no position independent code
allowed, as the generated image often does not support short range
components reference.
BUG=chrome-os-partner:31438
TEST=with the rest of the patches included MIPS board urara builds
successfully
Change-Id: I637dd44eb565447c18b2c3cdb022d0933c52fd20
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215677
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add basic board support for the ImgTec Danube Virtual Platform, which
emulates a system built around the Danube SoC.
Run this by loading coreboot.bimg into a flash device connected to SPFI1
chip select 0 & then executing the Danube boot ROM.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add build infrastructure and basic support code for the ImgTec Danube
SoC. This support is sufficient to run on a simulator.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207974
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new utility named bimgtool, a simple tool which generates boot
images in the BIMG format. This is the format the Danube boot ROM
expects the user supplied code to be wrapped in, it is described by
struct bimg_header in the code.
This utility will be used to wrap the coreboot bootblock when building
Danube targets.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I63b9f5e09cd1f12765317b38e2a0dd033cdd6d39
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207975
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In addition to ARM based systems, allow MIPS based systems to select
bootblock console support.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-on: https://chromium-review.googlesource.com/207973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
The power button signal is driven from the silego part.
It's active high when the button is pressed.
BUG=None
BRANCH=None
TEST=Booted with power button pressed. vboot saw the press and
requested a shut down.
Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214847
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of calling out the gpio index and port numbers use
real names. It's semantically clearer and there's only one
place to adjust the hardware values.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted.
Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215542
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The 64 bit division function is not readily available from the MIPS
toolchain inside chroot. This causes link failures when building
upcoming MIPS coreboot targets.
It turns out that the only place using the 64 bit division is the
printf formatter when processing the '%L' format specification.
Further examining of the source code has shown that so far the '%L'
format specification is used only in x86 code.
The suggested fix is to suppress %L support for MIPS.
BUG=chromium:406038
TEST=with this patch the upcoming MIPS platforms build successfully.
Change-Id: Iec0123620ac84a1697892f995235511b3288d4b2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214174
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the build infrastructure and basic architectural support required
to build for targets using the MIPS architecture. This is sufficient
to run on a simulator, but will require the addition of some cache
maintenance and timer setup in order to run on real hardware.
BUG=chrome-os-partner:31438, chromium:409082
TEST=none yet
Change-Id: If4f99554463bd3760fc142477440326fd16c67cc
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207972
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this change reduces the code duplication of the bootblock and the romstages for
Nyans.
BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Reviewed-on: https://chromium-review.googlesource.com/214050
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
vprintk is created out of do_printk for all the archs.
BUG=none
TEST=Built Nyans, Falco, and Ryu. Verified serial output on Blaze and Falco.
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Idf708359f0e9e9a9f32a601a5a117e469d5025ba
Reviewed-on: https://chromium-review.googlesource.com/214566
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
1. Fixed some errors in selftest compare to crb
2. Some WA steps for xhci in sleep trap is only for lpt
BUG=chrome-os-partner:28234
TEST=compile ok, run selftest on auron to verify
boot to OS
BRANCH=None
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Iaccb087581d5f51453614246bf80132fcb414131
Reviewed-on: https://chromium-review.googlesource.com/215646
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Tested-by: Kane Chen <kane.chen@intel.com>
Microcode released on August 29.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus with E0 step
Change-Id: Icf90b2fb3c70b1edae4979f8e491fe98a6766e95
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215680
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Allow more flexibility by reading and writing to system registers at current
EL. Instead of specifying what _ELx register to write to, code can specify
_current.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles and boots to kernel on ryu
Change-Id: Ic1d9e18e6fc016a04f17621a148e62d6cbd04ce7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214577
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209465
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
In order to ease the process of reading and writing any register at current EL,
provide read_current and write_current assembly macros. These are included in
arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow
the same header file to be included by .c and .S files.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully for ryu
Change-Id: I678ab89c4aa1b08898166e135b5ab2d6453bb5e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214576
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Add library helpers to access standard arm64 registers. This library also
provides functions to directly read/write register based on current el. So, rest
of the code doesnt need to keep checking the el and call appropriate function
based on that.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Libpayload and depthcharge compile successfully for ryu
Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The kernel doesn't have the logic for bringing up the plld.
Therefore, configure it in the firmware. The clock used
is an interim value until the display controller sequencing
is fully implemented.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Noted configured freq is close to requested. Also, no
more plld errors observed from the kernel.
Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214841
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Depending on the requested frequency the plld cannot
necessarily obtain the exact clock. Therefore provide the
closest configured frequency as a return value. This is
equivalent to the t124 patch.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Built and noted plld actual value close to requested.
Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214843
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
These symbols should have been removed with the stack
refactoring. I'm not sure how it was missed.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel with both cpus.
Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215541
