Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update the verb count.
TEST=build/boot Win11, Ubuntu 25.04 on Starfighter RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I2b96318df4431bc155af5a8f92935900031e0bfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update verb count. Add HDA verbs for Intel IGD HDMI audio
output.
TEST=build/boot Win11, ubuntu 25.04 on Starbook TGL, verify all audio
inputs/outputs function as expected. Verify verbs loaded via cbmem log.
Change-Id: Id9a08c8bd32e0c75f92e8d6b3b8ff6c033608a4f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I4ccc604f7db4ec85d8e5f311c7f8fd5c913ec04b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89082
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.
TEST=build/boot Win11, ubuntu 25.04 on Starbook MTL, verify all audio
inputs/outputs function as expected. Verify verbs loaded via cbmem log.
Change-Id: I0805d943009de1963c8e6da5acf56dd7a5ea83ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89081
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook KBL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I3cf96ce12250d6a5cd7afa39070681606266fb2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update the verb count.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook CML, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I1ee05afe9805ca6531d49150f1ead8722c4393b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89079
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook ADL-N, verify all audio
outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: Ie0961a6ebc4aa8df0c2fedeff8fd5bacd16fc01e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89078
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook ADL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I728c835361f1fa6fe813255973b33131e2a008e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Kelsier shares the same firmware with Kaladin so coreboot loads the same
loader firmware to ISH. Since Kelsier is a sensor-less design, change
it to load lite_ish.bin and disable ISH related GPIOs depending on
firmware config.
BUG=b:441613379
TEST=flash and boot to DUT, check suspend function works normally on
kelsier
Change-Id: I04c77db813fcd993217b5c366872cc583e265939
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.
Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.
Ref=858124 Power Delivery Guide Rev1p0
830097 Powermap Rev1p1
BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error
[ERROR] Could not find the SKU power map
With the current patch this error line is not seen in the CPU log
anymore.
Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
As per Intel document 853127, EPD_ON_GCD_OUT (previously GPP_A15)
is no longer available for other functions. Updated GPIO
configuration accordingly.
Reference: Intel doc 853127
BUG=none
TEST=Build and boot test on fatcat hardware
Change-Id: Ie4a3967ceecd10905ba0424d85d8f1392625bf16
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89103
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the matsu variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.
BUG=b:443612246
TEST=1. util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_MATSU
2. Run part_id_gen tool without any errors
Change-Id: I81d010fdda927db56d7b41ddc527c1c40b2cf768
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update GPIO_PCH_WP configuration for trulo varaints as the value
in the baseboard is changed.
BUG=b:443677716, b:435612546
TEST=Build uldrenite, pujjocento and orisa firmware successfully
Change-Id: I7fb35091000b1df1b8008f26488e9290be3efe2d
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Change GPIO_PCH_WP from GPP_E3 to GPP_E12 to align with trulo
reference hardware schematic.
BUG=b:443677716, b:435612546
TEST=Build pujjolo and kaladin firmware and verify SPI ROM
write-protect
Change-Id: I935d74cb5447f45f297fe45506c14623095d7127
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89117
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change stylus gpio and wake source setting to let eventlog could
show GPE #12 message when interrupt suspend by stylus.
BUG=b:439761057
TEST=Build and boot to OS, do the suspend_stress_test and check
eventlog show wake source information. And do warmboot/coldboot/
suspend 500 times stress test all pass.
Change-Id: I8d16e867fd56f1072b09bb6ab71b6d08a7d38376
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89129
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
Uldrenite14 need to set this config since we use unified firmware
for UFS and eMMC skus.
BUG=b:437006063
TEST=emerge-nissa coreboot
Change-Id: I86f41a4e6c9c136f031eb3813efa3c06043237b9
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88932
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a wake configuration to the cnvi_bluetooth device for
all the ptlrvp board variants. The "wake" setting is now registered to
"GPE0_PME_B0" using the common CNVi block. This enhancement ensures that
the cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I4c17ca926a4409cedfaef24a802330ef463703ac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
During the ACPI initialization phase at boot, the driver
is pulled, causing the LED of the WFC camera flash.
This issue can be resolved by replacing GPP_D15 with
GPP_D16 in the mipi settings.
BUG=b:434106137
TEST= Build and boot to OS, and check the Chromebook
logo will not flash
Change-Id: I2fce7f7c9c5c852efbdef3e5ef757cab3433f4c6
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89014
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the new memory support: Hynix H58G56CK8BX146
BUG=b:444335746
BRANCH=firmware-brya-14505.B
TEST=Run part_id_gen tool and check the generated files.
Change-Id: Id473adafffc1dabcb8f8e9a1f548966a0ba5a334
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89147
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the parade
touchscreen (PRT3406) device, connected to I2C bus 24.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:431660019
TEST=emerge-nissa coreboot and parade touchscreen can work well
Change-Id: Iaaf740032de973461b616e186ac628436cbbc2a5
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
BUG=b:440996061
TEST=Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.
Change-Id: If0997ecb43eb5f687f1416abe42764fa31b1eaf5
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add the memory parts: H58G66CK8BX147 (Hynix) in mem_parts_used.txt
,and generate SPD id for the parts.
BUG=none
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I485d8f947b6d8efc5b43ea1ddf1e4187eb4cf2bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable LFP1 as it is not present
Change-Id: Ib998bc6df5430d08f9ded4d1e84f5aaa57b8be3d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89097
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFP3 as it is not present
* Change eDP panel colour depth from 18-bit to 24-bit (8 bpc).
* Change POST brightness from 255 to 100.
* Change minimum brightness from 6 to 0.
* Change DPST aggresiveness to 6 to 2.
* Enable PSR
Change-Id: I895fc61dff120e0ae989f45b37c0c5cde3c5e2ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the ojal variant of the ocelot reference board by copying the
ocelot files to a new directory named for the variant.
BUG=b:437459757
TEST=1. Build emerge-ocelot
2. Run part_id_gen tool without any errors
Change-Id: Ic2fc86d89facae21b9bed898ebe518d316d953da
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Added support for new mainboard configurations, `ptlrvp_chromeec4es`
and `ptlrvp4es`, to the Intel PTLRVP platform. These configurations
extend the existing options for pre-production silicon of the
Panther Lake SoC.
BUG=none
TEST=Build with new configurations to ensure successful compilation and
correct feature selections.
Change-Id: I3f716ab71a97d02b1694858d966f8111f18adff3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88997
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook KBL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: I4d4a41736faac944b3165a56fe5846f24c20f549
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook ADL-N, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: If91c723b6a2fa145c640e06a21198c5ff30a34f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove presence detection flag for the DMIC and internal speakers.
Update the subsystem ID to match that used by the AMI UEFI Firmware.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook MTL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: I7621a6b57fb525892e84d06470eab5a9bdd32065
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89042
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Raptor Lake FSP doesn't seem to honour not touching GPIOs, so set
this to avoid major issues such as the SSD not being recognised and
causing an indefinite hang.
Change-Id: I50edc788c7a4c6ee5a2d74aa76b9e33fb56ed15e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit adds a call to disable_slow_battery_charging() in the
lb_add_boot_mode function.
The logic ensures that charging is disabled if the system is booting in
a normal mode, where neither the LB_BOOT_MODE_LOW_BATTERY nor
LB_BOOT_MODE_OFFMODE_CHARGING flags are set.
This prevents unintended charging by the AP firmware when the device
is not in a low-battery state or booting from off-mode charging to
avoid battery unmanaged health related problem.
TEST=Able to build and boot google/quenbi.
Change-Id: I648dc72a35ad2773f803792248fa87351333828f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89023
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change implements `lb_add_boot_mode` for the `bluey` mainboard,
which adds the platform's boot mode information to the coreboot tables.
This is done by checking the EC (Embedded Controller) to determine if
the battery is below a critical threshold.
If the battery is critically low, the `LB_BOOT_MODE_LOW_BATTERY` flag
is set. This information is then passed to the payload, allowing it to
take specific actions, such as displaying a low-battery charging
screen.
TEST=Able to build and boot the `bluey` mainboard.
Change-Id: I473cec7645954e753e160467aa8b83b67b28ab76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the new memory support: Hynix H58G56CK8BX146
BUG=b:442335706
BRANCH=firmware-nissa-15217.B
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I8002c2c8e89882f4a705c7aae881544009f84e3b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit updates the GPIO configuration for the Ocelot baseboard
variant. It changes the definition of `GPIO_SLP_S0_GATE` from
being not connected (0) to `GPP_C08`. This GPIO will be used as
an indicator for the EC.
References:
- Schematic version: schematic_1433518
BUG=b:440270606
TEST=Perform an S0ix sequence on the system and verify that the
power state is properly reported on the EC console.
Change-Id: I303322f233824e6980ff6078e62f66eba36203ed
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88875
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new function, disable_slow_battery_charging, to
disable charging on the Bluey mainboard. This function writes a disable
command to the SMBUS chargers, turning off the charging process.
Additionally, this patch makes the following changes to support this
new functionality:
- The charging.c file is now compiled in both the romstage and
ramstage phases.
- The new disable_slow_battery_charging function is declared in
board.h.
- A new charging_status enum is introduced to clearly define the
charging states.
These changes ensure that the system can now properly control charging,
allowing it to be disabled when necessary.
BUG=b:439819922
TEST=Able to build and boot google/quenbi.
Change-Id: Ic0c59e0509889e6d166becf76279718b853021cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89022
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
