Currently, display_startup() is called unconditionally during
mainboard_init(). For normal boot paths, this can lead to unnecessary
latency (40ms) issues.
Modify the initialization flow to:
1. Initialize display early only for low-battery or off-mode
charging paths to ensure the user sees the charging UI.
2. Defer display initialization for all other modes to a new
mainboard_late_init() function.
3. Use a static flag (display_init_done) to ensure display_startup()
is only executed once regardless of the entry point.
TEST=Verified bluey still shows charging animation when low on
battery and boots to OS normally. Able to save 40ms of the boot time.
Change-Id: Id6bdda90b7f67c13cd7334ba17131a8243af0cdb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91845
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The URL must have the .pdf extension now, otherwise gets a 404.
Add a note on later revisions of Sure Start.
Change-Id: I00ab30b461795c672890a21d1fb2af929865c822
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Khalifa Rouis <khalifa@missingno.tech>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Default-enable CONFIG_TCG_OPAL_S3_UNLOCK for Star Labs boards so NVMe
OPAL devices can be unlocked via SMM on S3 resume when the payload
provides the password for the current sleep cycle.
TEST=build/boot adl/hz and starfighter/mtl with TCG enabled, suspend,
and verify SSD can be read after resume.
Change-Id: Ic3d9611295b1bdf9ea49cd6d4d6c924f8eafd746
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91046
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OPAL S3 unlock may run before an RTD3 NVMe is powered on. When the
storage root port uses the RTD3 ACPI driver, trigger the OPAL unlock SMI
at the end of _ON once the port has powered the device.
Do not rely on _ON being invoked during S3 resume. Always trigger a
best-effort unlock during the coreboot resume path. If the NVMe init
path fails (rc=1), keep the sleep cycle armed so a later trigger (e.g.
RTD3 _ON) can retry the unlock.
TEST=tested with rest of patch train
Change-Id: If83b59973ad878c31e19d146fec8bdbb6406ec2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91416
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide common entry points for the OPAL S3 unlock feature and wire them
into the generic x86 SMM and S3 resume code.
- Add opal_s3_smi_{apmc,sleep,sleep_finalize} helpers.
- Call these helpers from the default weak mainboard SMI hooks when
CONFIG(TCG_OPAL_S3_UNLOCK) is enabled. This keeps the feature usable
without forcing boards to implement new SMI handlers.
- Trigger the SMM unlock on S3 resume from arch/x86/acpi_s3.c.
Select SMM_OPAL_S3_STATE_SMRAM so the secret is persisted across SMM
handler reload. Add a delay and retry loop before unlock, and restore
NVMe BAR0 if the device loses PCI config state across S3.
The SMM side continues to whitelist only the OPAL service and unlock
APMC commands and fails closed if any invariant is violated.
TEST=tested with rest of patch train
Change-Id: I86a44760a189219a95914bd3549997880fb0242b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91045
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes commit "util/amdfwtool: Move APOB_NV quirk to amdfwtool.c".
Allow the AMD_BIOS_NV_ST and AMD_BIOS_APOB_NV to end at 16MiB.
Fixes a build failure when the region is last in the FMAP.
Change-Id: Icfa5b74e98223ff5864299d4e9a2d23606935b80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91820
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Applying the attribute silences the following error and allows
compilation with GCC 15.2.
error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute
Change-Id: I33cf3219f34e297de03f67d3e73058b10930c9f8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
PSP supports A/B updates of the PSP directory structure. This
is unrelated to VBOOT's A/B update scheme. At boot the PSP
structures of partition A are verified. If A is found corrupted
partition B will used to read in the PSP files. x86 software can
then fix the A partition and switch back to the A partition.
Add functions to get, set and toggle the active boot partition used
on the next boot.
Change-Id: Ia7f2eedae5b277745cb34a0761bd1a8b61441695
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Implement the red i-dot LED in the ThinkPad logo at the display lid.
On warm reboot the LOGO LED isn't automatically turned on by the EC.
Turn it on in the ramstage code, which allows to see when the reboot
has happened. (Similar to PWR LED; see change ID 88998)
Further testing on other devices running H8 EC is required!
TEST=LOGO LED is on after warm reboot on Lenovo T440p.
Reference: https://ch1p.io/t440p-leds-control-linux/#list-of-leds
Related: https://review.coreboot.org/c/coreboot/+/88998
Change-Id: I2ebba5a4c1ffc38f0c2e1b24793e4a252cc171bd
Signed-off-by: Christian Schrötter <cs@fnx.li>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91837
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Star Labs boards can continuously trigger the TCO intruder SMI.
Default the common Kconfig symbol off to avoid those spurious events.
Change-Id: I4fbdc3d0f43d814564e972afcaaac1e967fb49f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PWM_Frequency_03 changes from 200Hz to 2kHz.
The 16-inch QHD panel supports 200Hz to 2kHz, while the 16-inch 4K
panel supports 200Hz to 10kHz. Keep the shared board VBT at 2kHz for
now; the higher 10kHz value only applies to the 4K panel.
Change-Id: If5a6d1ea248132219f8c0115771fb26d9d5b228a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91870
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 2kHz.
The 14-inch 1080p panel supports 190Hz to 2kHz, so use the panel's
safe maximum instead of the old 200Hz default.
Change-Id: Ibf21bf291fecfd2b10a74bb3667549ef2f271356
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The 14-inch 4K panel supports 100Hz to 10kHz, so raise the board VBT
value to the panel's safe maximum.
Change-Id: I94694d06e09d58f92966a2c827aad52f15e1e4c6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91868
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The 12.5-inch 2K panel supports 100Hz to 10kHz, while the 12.5-inch
3K panel supports 200Hz to 25kHz. Keep the shared board VBT at 10kHz
until panel-specific selection exists.
Change-Id: Ia8bf5a324eb65698a8ba89b89cee8a9d10fba07d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91867
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The HZ panel is validated at 10kHz, so use that known-good value in
the board VBT instead of the old 200Hz default.
Change-Id: Ieaddba9a7fef42be8de2cc64f234a39dde62c25f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Restore the HZ panel VBT minimum brightness for panel entry 03 to the reference value.
Post_Min_Brightness_03 changes from 0 to 25.
Change-Id: I04ae425a1377b4a716127a0624872b74fb3eb962
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the StarBook 14-inch 1080p panel VBT timing values against the
panel datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: Ie153c6272595268565e1966b7d7773d4d068680c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91864
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the i5 panel VBT timing values against the panel datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 2000.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.
Change-Id: I717be5863d0352224eae1053db77e8d3234a396f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the StarBook 14-inch 4K panel VBT timing values against the panel
datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.
Change-Id: I941e268f6a05f74248b19eb75fc7f07f781e347c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91862
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the StarFighter panel VBT timing values against the panel datasheets for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: I382a1609aa7fee082b172ed07c761a7655a56dd3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the HZ panel VBT timing values against the panel datasheet for
panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: Icc711c3c6f105cfd6fc1dc5bbab24d9b172a924f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91860
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gnvs.c uses the global NVS definitions directly, so include
acpi/acpi_gnvs.h explicitly instead of relying on indirect headers.
Change-Id: Ifd19111a01ced3cb9bdb85ac192358e823dd3f44
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91857
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MKBP support for zork devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/morphius, verify vivaldi keyboard mapping
functional under both Linux and Win11.
Change-Id: I021454b92cdb90e2a385eee1b3d4cc0438c75132
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for reef devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/reef, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: If7a8df8469c22404e22d80fd4d116b862b6b5cec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91786
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MKBP support for octopus devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/ampton, verify vivaldi keyboard mapping
functional under both Linux and Win11.
Change-Id: I31ecd87d8e9335dd4131f022370b32bf2d056b03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for hatch devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/akemi, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: I7bd222160efdd4de0d63ab9542c0d2828aac583a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for glados devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/chell, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: Ia1ea5cdece52d33f7467af0b6e1d891a04b63b94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Allocate resources to devices on the bus.
This booted to the fedora disk image using nvme with the CrabEFI payload.
Change-Id: I898b38fd4fa94f7d1a73132d6f821ff7c9e201dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
cbfstool/flashmap/kv_pair.h uses the `__printf` macro. So we need to
include the header file defining `__printf` in the compilation.
The tooling can now be compiled on its own outside the coreboot build
system.
Change-Id: I5a622b50684c42773e66e6d9145d5de9858c9e9a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91887
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using a signed, non-fixed-width type for bitfields can cause problems.
So, use uint8_t since the affected bitfields occupy exactly one byte.
Change-Id: I728072b10baf77819a387df76b588b6a826e2841
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91855
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The CPUCP (CPU Control Processor) binary is currently stored
uncompressed in the RO region. To save space in the RO section
while maintaining fast boot performance in normal mode, split the
CPUCP CBFS entry into two distinct files:
1. cpucp_rw: Stored in FW_MAIN_A and FW_MAIN_B with no compression
for performance.
2. cpucp_ro: Stored in the COREBOOT (RO) region with LZMA
compression to save flash space.
Update the loading logic in cpucp_load_reset.c to select the
appropriate binary based on the current vboot mode (Normal vs.
Recovery).
BUG=None
TEST=Verified that CPUCP loads from 'cpucp_rw' during normal boot
and 'cpucp_ro' when vboot recovery is triggered.
Normal Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_rw' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Recovery Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_ro' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Change-Id: Iec5294beec4377b13f8b7354d86055d5907c6556
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This pulls in the following change from the submodule:
- add binaries for V2000A
Change-Id: I606f7926bcdef2a02ed1f492f37a0d7aefa27714
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91856
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
aarch64-elf nm doesn't support '--no-weak'. Replace the 'nm --no-weak'
call with 'grep' with "[TDRCB]" pattern to collect the non-weak
symbols.
Change-Id: I19195034b31f39086946b7e5ee15317d6f5dd880
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On Faegan the FSP supports RAS. Allow the user to configure
RAS features and pass them to the FSP using UPDs.
Change-Id: Ia7091d216a446d56632e64f9bba0e2a166410139
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Create the dirkson variant of the dirks project by
copying the files to a new directory named for the variant.
BUG=b:494049087
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_DIRKSON
Change-Id: I7e1257ebe8292e00a282eb75535466dcb2b459eb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on eldrid, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I65832388649daceb498c91e6405d2b8343ca2aeb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on magolor, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I6853465ba77be1f95cbe5795b318df02ecc1da39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91798
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on taeko, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: Ie26cd77c8a58034dbce05a1ab308b9dcc122484c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91797
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TMBC support has been backported to the EC firmware for CYAN
and KEFKA, so add SCI support for the MODE_CHANGE host event.
TEST=build/boot Win11, Linux on CYAN, verify tablet mode switching
functional via Intel VBTN driver.
Change-Id: Id3474e07bad1b6371644821dfe39a8105e4dd0f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Volteer-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Set the default SYSTEM_TYPE for non-convertibles to LAPTOP as
is done for most newer ChromeOS boards.
Change-Id: I02337464953fdb654e99019af4d2f142e1910e97
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Reef-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: Iff5c8379ff318a5616fee0133fef6f0ad9b93003
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Octopus-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: I298fb413480f6392990d00dc375db4d1e4176d9d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Hatch-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: I8b72efb176087dda29b1c32b7ceef4c4544ef4d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91748
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for the CAROLINE variant so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI.
Change-Id: I67429b34a197cb4f1e3938040b0b1853462796c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Dedede-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Adjust the system type check in mainboard_init() to account for
both laptops and convertibles.
Change-Id: I8cce636eb7e8ae6dfe16d6cd5004f463b5a7dd2d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91745
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for Brya 360/flip variants so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI (VBTN).
Change-Id: I84bfd1df72d24b717f2b89906fd8dd2bef38d2b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Introduce EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS to control inclusion of
Intel VBTN and AMD VGBI ACPI devices used for tablet/convertible mode.
Default is y for non-ChromeOS builds when the board selects
SYSTEM_TYPE_CONVERTIBLE or SYSTEM_TYPE_DETACHABLE.
Add vbtn.asl (Intel INT33D6/INT33D3) and vgbi.asl (AMD AMD33D6/AMD33D3).
In ec.asl, gate VBTN/VGBI notify and these includes on the new config.
Boards that are convertibles or detachables will enable the vendor
tablet controls by selecting the appropriate SMBIOS enclosure type in
subsequent changes.
Change-Id: I208c1f1856a9223af5109464ecf316e76de3a976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
In scenarios where the system is booting with a critical or low battery,
lowering the initial CPU frequency helps reduce the instantaneous power
draw, ensuring the battery can sustain the boot process while fast
charging is being enabled.
Changes:
- clock.h: Replace 806MHz (0x2A) with 710.4MHz (0x25) based on 19.2MHz
XO.
- mainboard.c: Update handle_low_power_charging_boot() to use the
new L-VAL and update the debug log accordingly.
BUG=b:436391478
Change-Id: Ida30824e344a4613c797083711c3f6ee31f9694d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
During certain boot sequences, such as low-battery or off-mode charging,
automatic USB Type-C port resets initiated by the ADSP can cause
unnecessary power fluctuations or connectivity drops.
Implement adsp_skip_port_reset(), which toggles the SKIP_PORT_RESET bit
in the PMIC_PD_NEGOTIATION_FLAG register. This bit informs the ADSP
firmware to bypass its default port reset logic. Use this during
low-power charging initialization to ensure a more stable boot process.
BUG=b:436391478
TEST=Verify no unexpected port resets occur during Google/Quartz boot.
Change-Id: I215a1806799a10355dd36b483f8d441f615f5258
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91666
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support to drop the CPU frequency to the minimum
806 MHz when the device enters OFF‑mode charging, improving power
efficiency. The register details are available in the
HRD-X1P42100-S1 hardware document:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Tested by creating an image.serial.bin and verifying that it boots
on X1P42100 and the CPU runs at 806 MHz during OFF‑mode charging.
Change-Id: I8f0d5b598a4dad419195957be8b334a27ec18982
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
