These are the release notes planned to go out with the 25.06 release.
Note that we've removed the bugs section. We may look at adding
"Fixed Bugs" and "New Bugs" in the future, but it was depressing not
seeing changes between the releases.
Change-Id: I8cedbdb7b05605d1904446590fb25552a7e0c727
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88206
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old wiki no longer exists (see the announcement at [1]), the
current URLs lead to an HTTP 404.
To fix it, replace the URLs with the main page URL, which contains
links to the current documentation, manual, etc.
[1]: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/GNT23GQEQ5I5JCJ6YKUSRXD7JORSG4RV/
Change-Id: Ifb430a033d12f8064893f75315d577b5e78ffc9e
Signed-off-by: Raphaël Mélotte <raphael.melotte@mind.be>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This adds the release notes template for the upcoming September release
of coreboot.
Change-Id: I9033b107f148b4b40bb1243d2d0eb0b7e7f7b6dc
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Clean up section on flashrom vs flashprog
- Clarify flash regions and command used to flash `bios` region only
- Specify command used for external flashing
Change-Id: Icf464f4532b956731040fed97da0726856524c16
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently the SMMSTOREv2 only supports MMIO ROM below 4GiB. As the
space below 4GiB is typically limited on x86, add support for extended
MMIO ROM windows as found on recent hardware.
Allow the SMMSTOREv2 to be memory mapped above 4GiB by adding a new
field to the coreboot table called 'mmap_addr'. The users outside
of coreboot must check the size field of the coreboot struct to
determine if mmap_addr is supported. When it is it holds the
64-bit physical address to the MMIO ROM window.
The old 'mmap_addr' was renamed to 'mmap_addr_deprecated' to indicate
that it should not be used any more.
Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87114
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Use an additional Realtek NIC MAC programming sequence recently
added to drivers/net/r8168.c.
BUG=https://ticket.coreboot.org/issues/579
TEST=Specified MAC address now recognized and retained by Linux r8169
driver without further work.
Change-Id: Ia1409874920b2e598e8b8b3c186fc46bd0cef296
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87437
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule
was found, SMMSTORE SMI handler can use commands with the highest
bit (0x80) set to access the whole flash instead of just the SMMSTORE
region. The rest of the interface is identical to regular SMMSTORE v2
except for a new call to control full flash access.
The added call saves information about the availability of capsules in
SMM memory. The call is ignored when run more than once, meaning there
should be no way of enabling full flash handling after it was disabled
and vice versa. The call should always be made by the firmware to lock
further calls, so that an OS could not gain full flash access. This is
done on entry to BS_POST_DEVICE after capsules are obtained in
BS_DEV_INIT.
Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
- some formatting fixes;
- add information about proprietary blobs;
- update information about the tested hardware and operating systems.
Change-Id: I85a8f1df2ffc6e0e1674c4b82888a3964aa8d672
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Update the instructions for building the documentation to account for
the switch from Recommonmark to MyST Parser
- Update outdated URLs
- Update various details to account for the current behavior and
features resulting from previous changes
Change-Id: I569862e30fb88a421ad2338aafabeaf3ea76836a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
According to MediaTek's proprietary PI_IMG parser, two cookies (one
header and one footer) are expected. Therefore, add a script to perform
validity check of the PI_IMG firmware, so that format errors could be
caught in build time.
Change-Id: I27011492c7fab747aa3ee12d514d20a6a52d0a4d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87226
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow adding more scripts to the util/mtkheader folder, rename it to
util/mediatek. Also update description.md and regenerate
Documentation/util.md and util/README.md by util_readme.sh.
Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
As CB:71757 [1] updates Documentation/util.md and util/README.md
manually without modifying util/intelp2m/description.md, we port the
description changes back to that file.
[1] commit da54bd60af ("Documentation: Update information about
intelp2m")
Change-Id: I3d3f87517c445d650e9cea61448b28d005d46737
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87224
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This doesn't change any text - it just reformats the existing document.
- reflow paragraphs to 72 characters
- Put examples inside pre-formatted text blocks
- Adds spacing before section markers
Change-Id: I83925a4469e264da5887334e2584466cef089503
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.
Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Even when the identifier of an I2C device doesn't have a '0x' prefix,
it's still interpreted as a hexadecimal number.
Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In contracts to the ISA and LPC bus, eSPI doesn't support legacy
ISA-style DMA any more, so don't list eSPI as interface in the 'drq'
chapter.
The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI)
Interface Base Specification (for Client and Server Platforms)" revision
1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware
Hub (FWH) are not supported over this interface."
Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87204
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The line length limit in the commit messages is 72 characters, not 75,
so fix the value in the documentation. The 72 characters also matches
what checkpatch checks for.
Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This mostly lists things that long-time coreboot contributors already
do. Some of these rules were captured on the wiki. Others were adopted
from other git commit message guideline documents long ago.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic2ba681193e302318934cc2f7f30659eac73d099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75495
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since commit cd48d19836 ("Rename and move util/gitconfig/rebase.sh"),
the script util/gitconfig/rebase.sh was moved to
util/scripts/cross-repo-cherrypick.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibecafd6cca9d312c48cfc8c38ff11e686ee184d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87063
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch adds a section to the chapter 'Community' to clarify
coreboot's policy in regard to collaboration with other open-source
projects in the firmware space. It especially clarifies how coreboot
owned resources like servers and services the run can be shared with
partner projects and what the benefits and rules are for this
collaboration.
Change-Id: Ib9fbf91866192523d1a4914ff87e06f941f47d9f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are the final notes for the release.
Change-Id: I5daaae609b9271c543009c303db948fa7aa24b6d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87134
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generated by util/vboot_list/vboot_list.sh.
Change-Id: I079e02d24671a76520587b03a9d83fdc9f33e55b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
These are the release notes for the 25.03 release.
We will update again after the release is done with the final statistics
and information.
Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87042
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This adds the release notes template for the upcoming June release of
coreboot.
Change-Id: Ia8aa266973181be12620343eb58bb9ba8f0ccc79
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87030
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on a mix of existing P8x7x series boards, boardview, vendor
firmware dumps, and hardware testing.
Working:
- SeaBIOS 1.16.3 and edk2/mrchromebox/uefipayload_2501
- Serial port
- All USB2 & USB3 ports
- Z77 SATA ports
- Integrated graphics thru all ports with libgfxinit
- RTL8111F LAN (MAC address doesn't stick)
- Analog 7.1 audio out the back panel jacks
- Digital audio
- Front HDA audio panel
- PCIe x16 slot with nVidia 8800GT GPU
- PCIe x1 slots
- PCIe x4 slot with Intel Octane H10 1TB NVMe
- PCI slots
- Hardware monitoring and fan control
- S3 suspend
Untested:
- Hotplugging Z77 SATA ports
- EHCI debug
Not working:
- PS/2 mouse
- Wake on LAN
- Marvell SATA ports
Change-Id: Id9eef8b3426daecce0c95f56bfcd4caae2d52e50
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86172
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cleans up a nit identified by Martin when adding a very similar
variant.
Change-Id: Id19054c08643cf03b2afbfe4c8929ce9dacaea5c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
The pro_3500_series was converted to a variant to include the Pro 3400, so rename the corresponding documentation.
Change-Id: I5977f223d6f004a801e163397d1c97febd7ee1d4
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85846
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on autoport and HP Pro 3500.
As part of this change renamed 3500 to 3x00 and added this as
it's variant.
It's an almost identical board to the 3500 but has a smaller flash.
Other differences between boards were identified by autoport.
They may or may not important but were included anyway.
Tested on HP Pro 3400, behaves exactly as 3500 described in the docs.
Changes were not significant enough to require retesting on 3500.
Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Move x86_64 documentation to dedicated page
* Update with better description of current implementation
* Update TODOs
Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Implements a way for CFR options to depend on another option
being set to one or more specific values. This is achieved
by writing a list of values as a varbinary struct.
Change-Id: Iaf7965551490969052eb27c207fa524470d4dd6a
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Document the board and how to flash coreboot.
Change-Id: Id585b064054b338ea8cead6edb6c5153030b9cde
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Document the board and process of building/flashing coreboot on it.
Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81611
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
