This commit introduces support for touch functionalities on the
ocicat board. Changes include:
- Support for touchscreen devices in THC-I2C
- Wake support from S0ix state for touchscreen
- PMC GPE DW0 is reconfigured to GPP_F for Touchscreen in
variant.c for wake support
BUG=b:444942125
TEST= Build Ocicat and Test wake from S0ix state via touchscreen inputs.
Change-Id: Icf6fb0e170a64a5aec05590450a3bd40ab95cbf3
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Update the SaGV frequency registers in the devicetree as per
platform Plan of Record (POR) configuration:
- sagv_freq_mhz[1]: 3200 MHz -> 4800 MHz
- sagv_freq_mhz[2]: 6000 MHz -> 6400 MHz
- sagv_freq_mhz[3]: 6400 MHz -> 7467 MHz
The current frequency points were configured lower than the
platform's expected specifications.
BUG=None
TEST=Boot ocelot and verify that the system boots and MRC training
is successful for each SAGV point.
[SPEW ] Requested/actual ratio 72/72, Frequency=2400,
GearMode=1, RefClk=33MHz, tCK=3333333fs
[SPEW ] Requested/actual ratio 144/144, Frequency=4800,
GearMode=1, RefClk=33MHz, tCK=1666667fs
[SPEW ] Requested/actual ratio 192/192, Frequency=6400,
GearMode=1, RefClk=33MHz, tCK=1250000fs
[SPEW ] Requested/actual ratio 224/224, Frequency=7467,
GearMode=1, RefClk=33MHz, tCK=1071429fs
Change-Id: I7beab13bd9188aa47a45bc4a265aba75f00eded8
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90688
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Adjust the FMAP to match a newer version of the descriptor generated
with mFIT.
Change-Id: I546697f5c3352358a715f8783a7eda650c771c78
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90823
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the FMAP to match a newer version of the descriptor generated
with mFIT.
Change-Id: Id2eeec5269e8988e425e497f797645fa940922b3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move the code that configures power limits, tcc and other power related
settings into common code. The end result is the same, but the PL4 is
set by reading the battery capacity, rather than being hardcoded.
This patch also appends `_group` to each form group, to avoid conflicts
with objects now visible with the extra headers.
Change-Id: I41235039bc984686fa43f5c712e836d0b8d5d24a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89775
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the intermediate struct device's, and replace with the DEV_PTR
macro. This isn't a functional change, just cleaner.
Change-Id: I1a6a596a4d4215f6b670a8a7f7749a4f9bd391b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Ensure the board can boot by limiting the power limits if the battery
is missing. This addresses the factory use case for Wildcat Lake
processors.
BUG=b:None
TEST= Use cutoff at-shutdown and reboot
The device should boot with reduced power limits value and the log
is as shown below
[INFO ] Battery not connected, booting with reduced PL values
[INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (35000, 35000) PL4 (W) (45)
Change-Id: Iadb9c4c8450e6a55dd9fc644785742cc7aafd671
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90755
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO used for WOL was not configured to support WOL, so configure
this and adjust devicetree accordingly. Also, set the supported state
to S3, as coreboot disables this in S5.
Change-Id: Iaaac1aac3319473fe9e04f44043bf300620915cc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90791
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow payloads to run MIPI panel power-off commands, create a new
LB_TAG_PANEL_POWEROFF record and pass it to payloads.
BUG=b:474187570
TEST=emerge-jedi coreboot
BRANCH=skywalker
Change-Id: Ie11e1e78129188cc26d56764449fbafafa8fa316
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90768
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
- Increase the delay between romstage and ramstage GPIO init sequence.
- Delay the USB host initialization to meet the timing requirements.
BUG=b:475214332
TEST=Verify USB 3.0 storage key detection on Google/Quartz.
Change-Id: Ib6044b1e65fe0fe2fde5b688a9491d6e3fc75727
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90758
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On mc_ehl6/7 mainboards, the internal GPIO pull-up is required for the
SD card "Card Detect" signal to function properly.
This patch updates the GPIO configuration accordingly.
TEST=Booted mc_ehl6 and verified the voltage level at the
relevant pin before and after the patch.
Change-Id: I96a381f100dd9886ced030434316125d60a13a72
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90769
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this board, different I2C controllers must be activated and a
different RTC chip is used compared to mc_ehl1.
TEST=Booted into OS and verified that all relevant devices are detected.
Change-Id: If2990b7d8d599c6e5f5841d8018d2a3f00dbc515
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90766
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the PCIe root port settings, as the PCIe topology
differs from the mc_ehl1 mainboard.
TEST=Booted into OS and verifed that all relevant PCIe devices are
detected.
Change-Id: I0953a139b63080489128cc0a0dc865b65632b575
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90765
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard is based on mc_ehl1. As a first step, it contains a copy
of the mc_ehl1 directory with minimal changes.
Special adaptations for mc_ehl8 mainboard will follow in separate
commits.
TEST=Built siemens/mc_ehl8 successfully.
Change-Id: Icf8e90e7d3ed58ea4500cb6132fef37e32c5a4c2
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90764
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL update max TDP from 6W to 7W as requested by thermal team.
Increase tdp_pl1_override value from 6 W to 7 W.
Increase PL1 max power value from 6 W to 7 W.
The settings has been verified by thermal team.
BUG=b:476292154, b:476292156
TEST=emerge-nissa coreboot chromeos-bootimage
verified test result by thermal team
Change-Id: Iaedfb2caec589dd5f5be5cc872e302d55fa51dd6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add the trace length for the card reader USB port, and based on this
value adjust the macro used accordingly.
Change-Id: I1c7661f492b9193b75ed39abb2f5d14614cfc213
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `card_reader` option is only available on specific boards,
so to avoid enabling a USB port that isn't connected, set the
fallback value to 0 instead of 1.
Change-Id: Ied540d6242758663db7a7a11fbefb5c4a84b942d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90770
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This update introduces support for Google touchscreen devices
to the existing framework, enhancing compatibility with Google's
hardware interfaces. It extends the fw_config field with new
options to accommodate different connection types used by Google
touchscreens. Specifically, it adds:
- TOUCHSCREEN_LPSS_I2C_ELAN_REX for ELAN9006 interfaced via LPSS-I2C.
- TOUCHSCREEN_THC_SPI_ELAN_REX for ELAN6918 interfaced via THC-SPI.
- TOUCHSCREEN_THC_I2C_ELAN_REX for ELAN9006 interfaced via THC-I2C.
BUG=none
TEST=Connect Google's REX touchscreen with the conversion cables. Boot
to OS with fw_config setting for Google's touchscreen and verify
device enumeration in /sys/bus/hid/devices directory.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3fda0e4587d8484881c844674053a0badfc23a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89181
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard no SATA interface is assembled. Therefore, it is
deactivated.
TEST=Boot into OS and verify via lspci if relevant SATA Controller is
deactivated and no error in coreboot log is shown.
Change-Id: Iea01c30d18d81e67087ac8abef5cece0040087e5
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90730
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the unused GbE and PSE TSN GbE device 0. These devices are not
required for the current board functionality. Removing them simplifies
the configuration.
Also PSE is not used for any other functionality, the local host
interface is deacitivated as well.
TEST=Check if all other GbE ports of mainboard still work.
Change-Id: I83c7e9731d3684a0b0a7f16b533ee3ea2989f3c6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90726
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add AX211 wifi sar table for gothrax wifi sar config.
Use fw_config to separate different wifi card settings.
WLAN_AX211_Intel: 1
BUG=b:454207611
Test=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I11cf6cd61a13f5365530fc07b589d749c9459d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
`VBOOT_EARLY_EC_SYNC` enables EC software sync in romstage.
This is useful to achieve full USB-PD negotiation early in the boot
flow. It eliminates a problem where PMC is wrongly configured in
depthcharge during the EC-sync scenario which prevents USB devices
from getting detected when connected via a self-powered USB hub.
`VBOOT_EC_SYNC_ESOL` displays early sign-of-life (eSOL) during EC
firmware updates.
BUG=b:386920751,b:467506959,b:468885646
TEST=Verify detection and booting to OS from USB drive connected to
the Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Verify that eSOL is displayed during EC firmware update.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I612b4dc13be2efaee863e6cacf8fc4c432edc313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90762
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("S5VM17" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Ubuntu 25.10) on google/redrix, verify MIPI
camera functional under both OSes using the Intel IPU6 driver stack.
Change-Id: Ic72a96e93706c096b3839ab4c951e1d0a725b5ce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90744
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("CJFLE23" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Arch) on google/kano, verify MIPI camera
functional under both OSes using the Intel IPU6 driver stack.
Change-Id: I9232318c30ba0eee6dcd54f7199f6995a8ffa48b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90743
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As there is no model of the X280 with a dGPU, its devicetree does not
declare a device with a dgpu alias like the other Skylake/Kaby Lake
Thinkpad ports. This breaks the DEV_PTR(dgpu) reference in cfr.c,
causing the following build error if CONFIG_DRIVERS_OPTION_CFR is set:
In file included from src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:9:
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c: In function 'update_dgpu':
build/static.h:11:33: error: '_dev_dgpu_ptr' undeclared (first use in this function); did you mean '_dev_igpu_ptr'?
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
build/static.h:11:33: note: each undeclared identifier is reported only once for each function it appears in
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
make: *** [Makefile:431: build/ramstage/mainboard/lenovo/sklkbl_thinkpad/cfr.o] Error 1
Fix this by declaring a WEAK_DEV_PTR for the dgpu device, which will be
overridden by the compiled devicetree if the board variant declares a
dgpu device in its overridetree.
TEST=X280 builds successfully with the following defconfig:
CONFIG_VENDOR_LENOVO=y
CONFIG_BOARD_LENOVO_X280=y
CONFIG_DRIVERS_OPTION_CFR=y
Change-Id: I18cc18a88851bb943de8ab6d2d1fdcbf0f4aea86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90674
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Modify the Wacom digitizer HID to support the Samsung S-pen. This allows
a different driver to attach under Windows, which adds support for the
side buttons as eraser function and air command.
TEST=build/boot kahaku, verify S-pen works under Windows/Linux
Change-Id: I60b75f7f16f6bb028ad1747e78cc49cac810fc92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90735
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no wifi_mtcl.bin file publicly available, nor can it be
extracted from the stock Google firmware for YAVIKS, so restrict
USE_MTCL to downstream ChromeOS builds since validate_mtcl() fails
when no file is present in CBFS.
TEST=build/boot yaviks, verify no MTCL error in cbmem
Change-Id: I450db6fd8c460109aa4e491d88ec874c5f6429d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90734
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
All cyan-based boards define the size of the BIOS region in their IFD
as 6MB in size; it is likewise defined as such in chromeos.fmd. To
avoid having to override this in the board's config file when building
with a modern payload like edk2, set the default CBFS_SIZE to 6MB as
well to avoid issues with the payload not fitting.
TEST=build/boot google/edgar w/edk2 payload and default CBFS_SIZE
Change-Id: I17122aa2eb9848799c284d13d8c903ad125092b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90733
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CFR support was added in commit c1f0be39da ("mb/google/zork:
Add CFR option menu support"), a comma was inadvertently left off
the end the first CFR object in the list, which breaks compilation.
Fix this by adding the missing comma.
TEST=build/boot zork
Change-Id: I5f13d87cbc81f440b0c14d253a6334adab45631e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90732
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the board to perform a hardware reboot when the TCO watchdog
expires. This is achieved by using the default Kconfig option
SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN with 'n'.
TEST=Verified in the OS on mc_ehl7:
Checked IO-mapped register 0x408 Bit 0.
Without this patch, the bit is 1 (No Reboot enabled).
With this patch, the bit is 0 (Reboot on expiry enabled).
Change-Id: If3bee9db84c92480762f8a802031d2b01541dbdb
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
On this mainboard no RTC is assembled. Therefore, it is deactivated.
TEST=Boot into OS and verify if relevant I2C Controller is disabled and
no error in coreboot log is shown.
Change-Id: I23b4a735a09686fa2636280d7b410db59d884c49
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This new mainboard variant for the Siemens mc_ehl6 is initially based on
a direct copy of the mc_ehl6 configuration. This commit contains the
basic board setup with only minimal changes to enable the new variant.
Further specific adaptations for the mc_ehl7 hardware will be handled
in subsequent commits.
TEST=Build and boot to OS on mc_ehl7.
Change-Id: I46148492f65630175abb3ce884261d098314f2bc
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90714
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new Kconfig option to the ocelot mainboard
to enable VGA mode 12 support for early Sign of Life (eSOL).
- This option, `OCELOT_VGA_MODE12_SUPPORT`, is dependent on
`FSP_UGOP_EARLY_SIGN_OF_LIFE`.
- It selects `ROMSTAGE_VGA` and `FSP_VGA_MODE12` to enable the
necessary VGA components.
BUG=None
TEST=Verify VGA text rotation on ocelot RVP.
Change-Id: I71dff6e58c3e4487079c0090848ecde9da5153d7
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90731
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, Linux is unable to load the ISH firmware,
as GPP_F10 define lost
Update gpio pins GPP_F10 for ISH
bug=b:465776760
TEST=Flash and boot to OS on ocicat,
Verified ISH fw load in cpu console using below command.
~ # dmesg | grep ish
output:
intel_ish_ipc 0000:00:12.0: ISH loader: load firmware:
intel/ish/ish_wcl.bin
Change-Id: I4642560d3b14560e93158d1d19b496e22811600c
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90708
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the WiFi firmware configuration to add function for
getting WiFi SAR cbfs filename.
BUG=b:460231264
TEST=Build and check the system could boot to OS, and check the SAR table could work fine.
Change-Id: Ieec65debdc9f506e779352fcf8e54daa9296c0f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90376
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement mainboard_usb_typec_configure to program the Parade PS8820
retimers over I2C. The function sets the USB3 mode registers for
either normal or flipped orientation based on the polarity reported
by the SoC.
Additionally, update mainboard_init to perform standard I2C
initialization for the retimer buses when this feature is enabled,
ensuring the buses are ready for transactions during the USB
sequencing.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 00001203 00000000 00000000 00000000 ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000 ................
0a600430: 00001203 00000000 00000000 00000000 ................
```
Change-Id: I14f86945aeea9b83a9433edd53f5023231ca859d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90707
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the MAINBOARD_HAS_PS8820_RETIMER Kconfig option. This will
be used to conditionally enable I2C initialization and retimer
configuration logic on Bluey variants.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Change-Id: I949fb16f8c46a8375b50d2b108b8edde3231f4e9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90710
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This patch implements the power-on and reset sequence for the USB-C1
retimer on the Bluey mainboard.
Sequence Details:
- romstage: Added early_setup_usb_typec to ensure all power rails
(3.3V, 1.8V, 0.9V) are disabled and the retimer is held in reset
early in the boot process.
- ramstage (mainboard): Added setup_usb_typec to perform the power-up
sequence with the required 1ms delays between rails to ensure
hardware stability:
BUG=b:473489095
TEST=Able to detect USB devices in HS mode.
Change-Id: Ia93c0078aecdec98f3af28e73e7af5af7a3b20d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Convert MIPI camera configurations from static ASL files to devicetree-
based runtime ACPI generation using the mipi_camera driver. This moves
the camera IPU and device definitions from static ASL includes to
devicetree overridetree files.
Changes:
- Convert baseboard, voema, volteer, and volteer2 from static
mipi_camera.asl files to devicetree configuration
- Move IPU0 configuration with CAM0 and CAM1 to volteer/volteer2
variant overridetree files (baseboard devicetree not used directly)
- Remove all static ASL camera definition files (mipi_camera.asl)
- Simplify voema variant to use only 1 IPU port (CAM1 only) instead
of 2 ports, removing unused CAM0 port definition
- Add SSDB config based on sensor name/type and CIO2 config
This, along with follow-on patches, will allow volteer variants to be
properly supported under Windows/Linux as well as ChromeOS.
Change-Id: I7bd4ef2812a3d21b6541469bc3a126498d72f5ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The previous implementation violated ACPI spec by attempting to
implement a reset via _ON/_OFF, which are to be used exclusively for
device power management/power state transitions. As a result, under
Windows the CNVi BT device was continually re-enumerating and unable
to be used.
Fix this by moving the reset logic out of _ON/_OFF and into _RST, where
it belongs.
TEST=build/boot Win11 on google/taeko, verify BT device is functional.
Change-Id: I1627fefbf7747129344291cc8855c15dda50cf5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90582
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Remove unused I2C3 pin configurations.
- Remove RST control. The ETU925 fingerprint module does not
need to control the RST pin.
BUG=b:452542491, b:467835297
TEST=emerge-ocelot coreboot
Change-Id: Ib4db733187d1b15f89654b53c1cf98420d652546
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90696
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
and USB-C1 Retimer I2C access
Load I2C firmware to QUPV3_0_SE3 and QUPV3_0_SE7 Serial Engines and
configure both in MIXED mode to enable I2C access for USB-C0 and USB-C1
retimers.
Test=
1. Created image.serial.bin and verified successful boot on X1P42100.
2. Read the corresponding QUP SE firmware revision read-only register
and confirmed that the protocol field (bits 8-15) matches the
programmed value. Register details are in HRD-X1P42100-S1
documentation:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Example:If programmed as I2C, the register value read is 0x00000303,
where 3 denotes the I2C protocol.
Change-Id: I337329628ac04246ab579e062a802a028cb4c560
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90690
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the battery state-of-charge print statement in romstage to
include a percentage symbol. This makes the log output more
readable and consistent with battery level reporting.
Use '%%' to correctly escape and print the literal '%' sign in
the printk statement.
BUG=None
TEST=Boot Bluey and verify romstage logs show "Battery
state-of-charge 95%" instead of "Battery state-of-charge 95".
Change-Id: I97b533567b56bfaba41508e35a6f324f0dbf331e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90684
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The KLED VBT file is misconfigured and results in an error under Linux:
[drm] ERROR VBT has malformed LFP data table pointers
Inspecting the VBT using the Intel BMP tool reveals invalid data for
many of the panel definitions, as well as other settings.
KLED works perfectly fine with the kindred VBT, so use that instead.
TEST=build/boot Win11/Linux on KLED, verify display output works
properly.
Change-Id: I09aaa5c17517633fdae508239ecf8e72e3990e33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
