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mb/google/ocelot: Update sagv_freq_mhz as per platform POR config

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Update the SaGV frequency registers in the devicetree as per
platform Plan of Record (POR) configuration:

 - sagv_freq_mhz[1]: 3200 MHz -> 4800 MHz
 - sagv_freq_mhz[2]: 6000 MHz -> 6400 MHz
 - sagv_freq_mhz[3]: 6400 MHz -> 7467 MHz

The current frequency points were configured lower than the
platform's expected specifications.

BUG=None
TEST=Boot ocelot and verify that the system boots and MRC training
is successful for each SAGV point.

 [SPEW ]  Requested/actual ratio 72/72, Frequency=2400,
		GearMode=1, RefClk=33MHz, tCK=3333333fs
 [SPEW ]  Requested/actual ratio 144/144, Frequency=4800,
	        GearMode=1, RefClk=33MHz, tCK=1666667fs
 [SPEW ]  Requested/actual ratio 192/192, Frequency=6400,
                GearMode=1, RefClk=33MHz, tCK=1250000fs
 [SPEW ]  Requested/actual ratio 224/224, Frequency=7467,
                GearMode=1, RefClk=33MHz, tCK=1071429fs

Change-Id: I7beab13bd9188aa47a45bc4a265aba75f00eded8
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90688
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Appukuttan V K 2026-01-06 22:02:23 +05:30 • committed by Matt DeVillier
commit 63ec633ccd
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
View file

@ -35,13 +35,13 @@ chip soc/intel/pantherlake
register "sagv_freq_mhz[0]" = "2400"
register "sagv_gear[0]" = "GEAR_4"
register "sagv_freq_mhz[1]" = "3200"
register "sagv_freq_mhz[1]" = "4800"
register "sagv_gear[1]" = "GEAR_4"
register "sagv_freq_mhz[2]" = "6000"
register "sagv_freq_mhz[2]" = "6400"
register "sagv_gear[2]" = "GEAR_4"
register "sagv_freq_mhz[3]" = "6400"
register "sagv_freq_mhz[3]" = "7467"
register "sagv_gear[3]" = "GEAR_4"
# Enable s0ix