More complex systems, such as servers, have multiple IOMMUs. For
example, Turin CPUs have a total of 4 IOMMUs per socket. Abort IVHD
generation only if IOMMU is not present on domain 0. For other domains
simply continue the loop, so that other domains have their IOMMUs
described properly in the IVRS. To keep simple systems working as
before, IVHD generation is aborted, if IOMMU is not present in domain 0.
TEST=See IOMMUs on domains 1,3,4,6 being skipped during IVHD generation
instead of IVHD generation being aborted on domain 1 on
Gigabyte MZ33-AR1 console log.
Change-Id: Icd3a51621908dc3ee5c85aa1e5814f3b3ac69007
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89111
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces support for touch functionalities on the
ocicat board. Changes include:
- Support for touchscreen devices in THC-I2C
- Wake support from S0ix state for touchscreen
- PMC GPE DW0 is reconfigured to GPP_F for Touchscreen in
variant.c for wake support
BUG=b:444942125
TEST= Build Ocicat and Test wake from S0ix state via touchscreen inputs.
Change-Id: Icf6fb0e170a64a5aec05590450a3bd40ab95cbf3
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Update the SaGV frequency registers in the devicetree as per
platform Plan of Record (POR) configuration:
- sagv_freq_mhz[1]: 3200 MHz -> 4800 MHz
- sagv_freq_mhz[2]: 6000 MHz -> 6400 MHz
- sagv_freq_mhz[3]: 6400 MHz -> 7467 MHz
The current frequency points were configured lower than the
platform's expected specifications.
BUG=None
TEST=Boot ocelot and verify that the system boots and MRC training
is successful for each SAGV point.
[SPEW ] Requested/actual ratio 72/72, Frequency=2400,
GearMode=1, RefClk=33MHz, tCK=3333333fs
[SPEW ] Requested/actual ratio 144/144, Frequency=4800,
GearMode=1, RefClk=33MHz, tCK=1666667fs
[SPEW ] Requested/actual ratio 192/192, Frequency=6400,
GearMode=1, RefClk=33MHz, tCK=1250000fs
[SPEW ] Requested/actual ratio 224/224, Frequency=7467,
GearMode=1, RefClk=33MHz, tCK=1071429fs
Change-Id: I7beab13bd9188aa47a45bc4a265aba75f00eded8
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90688
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
As Panther Lake code is moving to a new phase, the full FSP headers,
including all the UPDs, can now be published. This CL is not tied to the
FSP update; it only provides the full list of UPDs for the current FSP
version 3442.07.
Details:
- FspmUpd.h : Expose all UPDs
- FspsUpd.h : Expose all UPDs
BUG=b:474393325
TEST=Build fatcat without any errors.
Change-Id: If02f9bf8d920497b0dcb52f5652839fae7fd0919
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90704
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Sowmya, V <v.sowmya@intel.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Occasionally when reading the EC version from ECRAM, the major
version fails to read and returns zero. To avoid having an incorrect
version reported, retry up to 10x with a 10ms delay between retries.
TEST=build/boot various Starlabs hardware, update the EC firmware,
verify the EC version is reported correctly every time.
Change-Id: I78d921e7230e8e180041097672661e744f70dde2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90834
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the FMAP to match a newer version of the descriptor generated
with mFIT.
Change-Id: I546697f5c3352358a715f8783a7eda650c771c78
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90823
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the FMAP to match a newer version of the descriptor generated
with mFIT.
Change-Id: Id2eeec5269e8988e425e497f797645fa940922b3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move the code that configures power limits, tcc and other power related
settings into common code. The end result is the same, but the PL4 is
set by reading the battery capacity, rather than being hardcoded.
This patch also appends `_group` to each form group, to avoid conflicts
with objects now visible with the extra headers.
Change-Id: I41235039bc984686fa43f5c712e836d0b8d5d24a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89775
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the intermediate struct device's, and replace with the DEV_PTR
macro. This isn't a functional change, just cleaner.
Change-Id: I1a6a596a4d4215f6b670a8a7f7749a4f9bd391b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Ensure the board can boot by limiting the power limits if the battery
is missing. This addresses the factory use case for Wildcat Lake
processors.
BUG=b:None
TEST= Use cutoff at-shutdown and reboot
The device should boot with reduced power limits value and the log
is as shown below
[INFO ] Battery not connected, booting with reduced PL values
[INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (35000, 35000) PL4 (W) (45)
Change-Id: Iadb9c4c8450e6a55dd9fc644785742cc7aafd671
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90755
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current implementation uses '%*s' which treats the calculated
str_len as a minimum field width. If the underlying string buffer is not
null-terminated, printk will continue reading past the buffer until it
encounters a null byte.
Switch to '%.*s' to correctly use the precision field, which specifies
the maximum number of characters to be printed from the string.
BUG=None
TEST=Able to dump FSP performance data with `DISPLAY_FSP_TIMESTAMPS`
Kconfig selected and meeting the FSP prerequisites. Verify that the
performance data table is printed correctly.
```
[INFO ] +---------------------------------------------------+
[INFO ] |------ FSP Performance Timestamp Table Dump -------|
[INFO ] +---------------------------------------------------+
[INFO ] | Perf-ID Timestamp(us) String/GUID |
[INFO ] +---------------------------------------------------+
[INFO ] 0 1242275 SEC/52c05b14-0b98-496c-bc3b04b50211d680
[INFO ] 50 1242282 PEI/52c05b14-0b98-496c-bc3b04b50211d680
[INFO ] 40 1242284 PreMem/52c05b14-0b98-496c-bc3b04b50211d680
```
Change-Id: Id95bd34b9c7d45d2c363339eb18adc5ac731c72b
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The GPIO used for WOL was not configured to support WOL, so configure
this and adjust devicetree accordingly. Also, set the supported state
to S3, as coreboot disables this in S5.
Change-Id: Iaaac1aac3319473fe9e04f44043bf300620915cc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90791
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD glinda up to 3 CS# lines are available. Drive the correct
SPI flash chip select using register 0x1d when necessary. This
allows to modifiy the contents of the "backup" SPI flash when
booting from the primary SPI flash.
TEST=Can access backup SPI flash on AMD Glinda SoC.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I446ef54a27c7a29155948cef9219cdef7b52b776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The PSP can choose the SPI flash to boot from. One such case
would be a corrupted EFS or invalid PSP directory tables.
Read the active SPI CS index from register SPI_ALT_CS_REG and
use it in boot_device_spi_cs().
Register name is taken from Linux kernel.
TEST=Booted on AMD/glinda with EFS on SPI CS0 corrupted. Will
boot from SPI CS2 and log shows:
spi_init: Booting from SPI CS2
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2c806d4d1563aa2403e84dec9f8768081e5e208a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To allow payloads to run MIPI panel power-off commands, create a new
LB_TAG_PANEL_POWEROFF record and pass it to payloads.
BUG=b:474187570
TEST=emerge-jedi coreboot
BRANCH=skywalker
Change-Id: Ie11e1e78129188cc26d56764449fbafafa8fa316
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90768
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add DSI power-off commands for TM_TL121BVMS07_00C, so that payloads can
run it to properly disable the display.
Also refactor the init commands using MIPI_DCS_* macros to improve
readability.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I0e7da1d23c658d7f3594cbb651c229057810319c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90740
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add verification to ensure that the integrated GPU is available,
avoiding crashes in FSP-M and FSP-S. The problem was first identified
on Skylake systems where the iGPU is missing or disabled, particularly
when VT-D is enabled, which can cause FSP-S to hang during boot.
Enabling SGX hides the issue, but it also leads to unstable
virtualization.
Apply the fix to Alderlake, Cannonlake, and Tigerlake SoCs in addition
to Skylake.
TEST=Build and boot to OS (Windows, Proxmox). Check to verify
functions work. (Skylake H110 + Xeon E3-1245 V5, E3-1260L V5,
i7-6700K, i3-7100)
Change-Id: I394f46ed5a277218a8dd587705eaecabe59fd110
Signed-off-by: Ulysse Ballesteros <ulysseballesteros@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89821
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
List of changes:
- Increase the delay between romstage and ramstage GPIO init sequence.
- Delay the USB host initialization to meet the timing requirements.
BUG=b:475214332
TEST=Verify USB 3.0 storage key detection on Google/Quartz.
Change-Id: Ib6044b1e65fe0fe2fde5b688a9491d6e3fc75727
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90758
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On mc_ehl6/7 mainboards, the internal GPIO pull-up is required for the
SD card "Card Detect" signal to function properly.
This patch updates the GPIO configuration accordingly.
TEST=Booted mc_ehl6 and verified the voltage level at the
relevant pin before and after the patch.
Change-Id: I96a381f100dd9886ced030434316125d60a13a72
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90769
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this board, different I2C controllers must be activated and a
different RTC chip is used compared to mc_ehl1.
TEST=Booted into OS and verified that all relevant devices are detected.
Change-Id: If2990b7d8d599c6e5f5841d8018d2a3f00dbc515
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90766
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the PCIe root port settings, as the PCIe topology
differs from the mc_ehl1 mainboard.
TEST=Booted into OS and verifed that all relevant PCIe devices are
detected.
Change-Id: I0953a139b63080489128cc0a0dc865b65632b575
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90765
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard is based on mc_ehl1. As a first step, it contains a copy
of the mc_ehl1 directory with minimal changes.
Special adaptations for mc_ehl8 mainboard will follow in separate
commits.
TEST=Built siemens/mc_ehl8 successfully.
Change-Id: Icf8e90e7d3ed58ea4500cb6132fef37e32c5a4c2
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90764
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD platforms the PSP can boot from different SPI CS lines
and do a recovery boot in case the default CS0 isn't usable.
Allow the SoC to provide the current boot_device CS line by
adding a new weak function.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9ed54b7979405d433f22458265f09701cda842e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For all functions which check flags, return a bool type instead of an
int type.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I39f0e2f392ec999f7622ed28c5755dd4d0eecf42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This CL update max TDP from 6W to 7W as requested by thermal team.
Increase tdp_pl1_override value from 6 W to 7 W.
Increase PL1 max power value from 6 W to 7 W.
The settings has been verified by thermal team.
BUG=b:476292154, b:476292156
TEST=emerge-nissa coreboot chromeos-bootimage
verified test result by thermal team
Change-Id: Iaedfb2caec589dd5f5be5cc872e302d55fa51dd6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit e59c5abd13 ("ec/google/chromeec: Add
EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC") refactored cbi_get_uint32() to
write directly to the caller's buffer instead of using a local variable.
This caused uninitialized memory (containing garbage addresses) to be
passed to the EC as the return buffer during CBI reads.
In the case of google/zork, the call to
google_chromeec_cbi_get_board_version() returned garbage data (e.g.,
0xae6ccd05 vs 0x5) which caused incorrect code paths to be taken:
- variant_override_gpio_table() selected wrong GPIO tables based on
invalid board version comparisons
- variant_touchscreen_update() skipped touchscreen GPIO configuration
because variant_uses_v3_6_schematics() returned true for garbage
values
- variant_uses_codec_gpi() returned wrong value, preventing
headphone jack interrupt setup
These misconfigurations caused input devices (touchpad, touchscreen,
trackpoint) to be non-functional, despite being detected by the OS.
The fix restores the original behavior by using a local variable
initialized to 0, ensuring a clean buffer is always passed to the EC.
TEST=build/boot google/zork, verify board version is read correctly,
all input devices functional under Linux/Windows.
Change-Id: Ia7be0bcc588075ab5c994edc3d68e979cc01ac79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the lb_panel_poweroff/cb_panel_poweroff structs to pass the
panel power-off commands from coreboot to payloads.
Also add mipi_panel_parse_commands() to libpayload libc, so that
payloads can utilize it to parse the power-off commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I652178c8075a1f3aee356502e682ef9a4f3d1cf8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the trace length for the card reader USB port, and based on this
value adjust the macro used accordingly.
Change-Id: I1c7661f492b9193b75ed39abb2f5d14614cfc213
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `card_reader` option is only available on specific boards,
so to avoid enabling a USB port that isn't connected, set the
fallback value to 0 instead of 1.
Change-Id: Ied540d6242758663db7a7a11fbefb5c4a84b942d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90770
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support for the Ibex Peak chipset was added in commit 888d559b03
("Support for Ibexpeak southbridge") by copy-pasting the bd82x6x
implementation and making appropriate changes. This resulted in some
of the PCI IDs for 6/7 series chipsets being left behind.
While some of these PCI IDs were removed in a commit b7d8788880
("ibexpeak/lpc: Fix PCIIDs."), there are still some that remain, we
remove those in this commit.
Change-Id: I5dc0e4fb2694eec9ef6246e0ae9211dff604d5b9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89569
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This update introduces support for Google touchscreen devices
to the existing framework, enhancing compatibility with Google's
hardware interfaces. It extends the fw_config field with new
options to accommodate different connection types used by Google
touchscreens. Specifically, it adds:
- TOUCHSCREEN_LPSS_I2C_ELAN_REX for ELAN9006 interfaced via LPSS-I2C.
- TOUCHSCREEN_THC_SPI_ELAN_REX for ELAN6918 interfaced via THC-SPI.
- TOUCHSCREEN_THC_I2C_ELAN_REX for ELAN9006 interfaced via THC-I2C.
BUG=none
TEST=Connect Google's REX touchscreen with the conversion cables. Boot
to OS with fw_config setting for Google's touchscreen and verify
device enumeration in /sys/bus/hid/devices directory.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3fda0e4587d8484881c844674053a0badfc23a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89181
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard no SATA interface is assembled. Therefore, it is
deactivated.
TEST=Boot into OS and verify via lspci if relevant SATA Controller is
deactivated and no error in coreboot log is shown.
Change-Id: Iea01c30d18d81e67087ac8abef5cece0040087e5
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90730
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the unused GbE and PSE TSN GbE device 0. These devices are not
required for the current board functionality. Removing them simplifies
the configuration.
Also PSE is not used for any other functionality, the local host
interface is deacitivated as well.
TEST=Check if all other GbE ports of mainboard still work.
Change-Id: I83c7e9731d3684a0b0a7f16b533ee3ea2989f3c6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90726
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add AX211 wifi sar table for gothrax wifi sar config.
Use fw_config to separate different wifi card settings.
WLAN_AX211_Intel: 1
BUG=b:454207611
Test=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I11cf6cd61a13f5365530fc07b589d749c9459d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
`VBOOT_EARLY_EC_SYNC` enables EC software sync in romstage.
This is useful to achieve full USB-PD negotiation early in the boot
flow. It eliminates a problem where PMC is wrongly configured in
depthcharge during the EC-sync scenario which prevents USB devices
from getting detected when connected via a self-powered USB hub.
`VBOOT_EC_SYNC_ESOL` displays early sign-of-life (eSOL) during EC
firmware updates.
BUG=b:386920751,b:467506959,b:468885646
TEST=Verify detection and booting to OS from USB drive connected to
the Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Verify that eSOL is displayed during EC firmware update.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I612b4dc13be2efaee863e6cacf8fc4c432edc313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90762
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Relocate the CBMEM top address from a hardcoded 0xC7800000 to the
start of the XBL log region (_dram_xbl_log).
This change moves the CBMEM region from the high Linux Kernel Reserve
block down into the lower DRAM Space 0, adjacent to other firmware
reserved regions. This consolidation prevents marking CBMEM range as
`reserved` and ensures CBMEM is placed in a more stable memory location
(marked available aka System RAM).
- Remove CBMEM_TOP define from addressmap.h.
- Update cbmem_top_chipset() to return (uintptr_t)_dram_xbl_log.
- Update memlayout.ld documentation to reflect the new memory map.
BUG=none
TEST=Boot on X1P42100 platform, verify CBMEM console and tables are
accessible and correctly located via 'cbmem -l'.
w/o this patch:
```
c7800000-cb7fffff : reserved
```
w/ this patch:
```
815a0000-819fffff : System RAM
```
Change-Id: I7392bb7a62d50640696301931940a7baa00351e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90760
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("S5VM17" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Ubuntu 25.10) on google/redrix, verify MIPI
camera functional under both OSes using the Intel IPU6 driver stack.
Change-Id: Ic72a96e93706c096b3839ab4c951e1d0a725b5ce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90744
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("CJFLE23" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Arch) on google/kano, verify MIPI camera
functional under both OSes using the Intel IPU6 driver stack.
Change-Id: I9232318c30ba0eee6dcd54f7199f6995a8ffa48b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90743
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As there is no model of the X280 with a dGPU, its devicetree does not
declare a device with a dgpu alias like the other Skylake/Kaby Lake
Thinkpad ports. This breaks the DEV_PTR(dgpu) reference in cfr.c,
causing the following build error if CONFIG_DRIVERS_OPTION_CFR is set:
In file included from src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:9:
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c: In function 'update_dgpu':
build/static.h:11:33: error: '_dev_dgpu_ptr' undeclared (first use in this function); did you mean '_dev_igpu_ptr'?
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
build/static.h:11:33: note: each undeclared identifier is reported only once for each function it appears in
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
make: *** [Makefile:431: build/ramstage/mainboard/lenovo/sklkbl_thinkpad/cfr.o] Error 1
Fix this by declaring a WEAK_DEV_PTR for the dgpu device, which will be
overridden by the compiled devicetree if the board variant declares a
dgpu device in its overridetree.
TEST=X280 builds successfully with the following defconfig:
CONFIG_VENDOR_LENOVO=y
CONFIG_BOARD_LENOVO_X280=y
CONFIG_DRIVERS_OPTION_CFR=y
Change-Id: I18cc18a88851bb943de8ab6d2d1fdcbf0f4aea86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90674
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a hooks that will populate mem_info structure with DIMM data
obtained from OpenSIL. As the memory population may be SoC-specific,
call a SoC-specific hook to fill the data.
Change-Id: I0b489c685877ac56f45e0e3abd0bd1b64549585b
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a Kconfg option to allow the SoC to add vendor specific
BERT entries, not yet defined in the ACPI spec. The function
only has to return the size of payload data and the generic
code will allocate space on the BERT table.
The caller must fill in all BERT fields since the generic
code doesn't know anything about the BERT entry.
Change-Id: I361700098ce1a3cc6acae991456a1901d2f07fb6
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90639
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 292d7b9d3d.
The resume failure is caused by the improper DEVAPC setting in fsp_init
for DM/PM and SPM. If fsp_init runs prior to dpm_init and spm_init, it
requires AP to grant the access to DM/PM and SPM from DEVAPC. The fix is
done in CB:90756.
BUG=b:474254985
TEST=Run suspend/resume test
Change-Id: Id21327f6d65d31659cdb8b4bda3b0a0510c438e8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
