Support oem_variables and change based on EC notify event.
BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot
Change-Id: Iac18cb968906a9dfe53836432ba8dbefee1dcc8e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86394
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table. For Panther Lake, remove "Die Management Unit (DMU)
load completed" and add "ESE completed AUnit loading" instead.
990:CSME ROM started execution 0
992:ESE completed AUnit loading 0
944:CSE sent 'Boot Stall Done' to PMC 174,000
945:CSE started to handle ICC configuration 274,000 (100,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 274,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 448,000 (174,000)
0:1st timestamp 556,874 (108,874)
BUG=b:376218080
TEST=Able to see TS elapse prior to IA reset on Fatcat
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84872
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code compiles and works fine in x86_64. Thus allow the user
to use x86_64.
TEST: Booted on amd/birman+ to OS using EDK2 as payload.
Change-Id: If1b5d91a376770c0f0e1a4ee46dd625b401fbfa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
On AMD platforms the SPI flash can be accessed using the ROM3
mapping in upper MMIO space. To reach the MMIO window the default
page tables must be extended to cover the address by default.
Add support for a SoC specific default address space being used on
x86_64, where the default of 4GiB/512GiB remains.
The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option.
Used in the following patch to use ROM3 mapping on AMD platforms.
TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ using x86_64
TEST: x86_64 still works on qemu/q35.
Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Currently, coreboot tries to manually probe the memory for
the Spike target as part of the SOC_UCB_RISCV target.
However, Spike already passes a pointer to the device tree,
so use it instead to get the memory size (like qemu-riscv does).
TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf)
Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43
Signed-off-by: joel.bueno <joel.bueno@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86588
Reviewed-by: Carlos López <carlos.lopezr4096@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Because the AGAH EC code is based on monitoring adapter current to
choose the corresponding DPTF OEM variable table, but not every
project follows this design. Based on the comment below, the AGAH
EC code was removed in 2023, so remove the AGAH DPTF OEM variant,
allowing each OEM to adjust in EC ASL accordingly.
BUG=b:394177292
BRANCH=None
TEST=None
Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86493
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newer verb for the ALC2669-VB6 from `starbook/mtl`,
as the current verb table failed to detect headphones being
connected.
Change-Id: Iaa50c6622f3ca75fbeff96300e08eb00e071c8b6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Use already defined macros in <spd.h> and <dram/ddr3.h>.
TEST=Built purism/librem_bdw (Librem 13 v1) with BUILD_TIMELESS=1, no
change in output ROM.
Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82315
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in
OS complaining about interrupt routing:
pcieport 0000:00:06.0: can't derive routing for PCI INT A
Tested on `starbook_adl` with Ubuntu 24.04 by running SSD
benchmark with GNOME disks and suspend.
Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The Fn key on pujjoniru emits a scancode of 94 (0x5e).
BUG=b:398943428
TEST=Flash Pujjoniru, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I8eb7f253a637741b0aa45aac4d1d59bd0309d559
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
According to the circuit schematic diagram, pujjoniru uses GPP_E17
as a write-protected gpio,so it is necessary to add the GPIO_PCH_WP
definition for GPP_E17 in gpio.h.
Duo to cros_gpios under variants/baseboard/nissa/gpio.c will call
GPIO_PCH_WP under variants/baseboard/nissa/include/baseboard/gpio.h,
causing our modifications to not take effect.
In order to achieve the above modification, we follow brya, we
modify DECLARE_CROS_GPIOS in variants/baseboard/nissa/gpio.c to
DECLARE_WEAK_CROS_GPIOS, so that the cros_gpios we defined in
/pujjoniru/gpio.c can overwrite variants/baseboard/nissa/gpio.c
BUG=b:396594296
TEST=wp status update verified by toggling it on and off.
Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86554
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit display UX message for low-battery shutdown using
platform_display_early_shutdown_notification().
This commit also enables the HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
Kconfig option, which is required for displaying the VGA text message
during early shutdown.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86476
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Refactor the FSP-M early Sign-of-Life (eSOL) implementation to utilize
the UX APIs defined in `ux.c`.
This eliminates redundant code and ensures consistent messaging during
critical boot phases, such as memory training.
BUG=b:339673254
TEST=Verified eSOL message over eDP while booting google/fatcat.
Change-Id: Icf22c39c21e2357b2a548398700a1488f4ef463a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch refactors the eSOL implementation for Panther Lake and
introduces two new APIs, mirroring those in Alder Lake, to manage:
- Low battery shutdown notifications
- Firmware update memory training
BUG=b:397302064
TEST=Built and booted google/fatcat successfully.
Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86509
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the SoC-specific implementation of the early
low-battery shutdown notification. The generic implementation now
resides within the FSP driver layer, requiring only platform-specific
customization.
Platforms can now implement platform_display_early_shutdown_notification()
when CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) is enabled. This
function utilizes ux_inform_user_of_poweroff_operation() to display a
"low-battery shutdown" message using libgfxinit.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: If9f68b2b5cc710e00584b451f904e60d724d1e32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86453
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an early low-battery shutdown mechanism during
FSP memory initialization. This is particularly important during
firmware updates, where memory training can consume significant power
and lead to abrupt shutdowns, potentially corrupting the firmware.
The changes include:
- Adding platform_display_early_shutdown_notification() to notify the
user of the impending shutdown.
- Checking platform_is_low_battery_shutdown_needed() to determine if a
shutdown is necessary.
- Implementing a shutdown sequence if low battery is detected during
memory init, especially when no MRC cache is found (i.e. firmware
update).
- Deferring shutdown on systems without MAINBOARD_HAS_EARLY_LIBGFXINIT
so that FSP-M (uGOP) can display a message.
This prevents firmware update corruption due to low battery.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86452
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit activates the Firmware Support Package (FSP) Memory
Sign-of-Life feature (FSP_UGOP_EARLY_SIGN_OF_LIFE), which allows for the
display of a user-configurable text message on-screen during memory
initialization. This feature enhances the user experience by providing
reassurance that the memory training process is underway and may take
some time.
The following FSP-M UPDs (Updateable Product Data) are utilized:
- VgaInitControl (boolean): Initializes graphics, establishes VGA text
mode, and centers the VgaMessage text on the screen. It clears the
screen, disables VGA text mode, and deactivates graphics upon exiting
the FSP-M (Firmware Support Package - Memory Initialization).
- VbtPtr (address): This is a pointer to the VBT (Video BIOS Table)
binary.
- VbtSize (unsigned integer): Indicates the size of the VBT binary.
- LidStatus (boolean): Given the limited resources available at early
boot stages, the text message is shown on a single monitor. The lid
status determines the most appropriate display to use:
- 0: If the lid is closed, display the text message on an external
display if one is available; otherwise, display nothing.
- 1: If the lid is open, display the message on the internal display;
if unavailable, default to an external display.
- VgaMessage (string): Specifies the text message to be displayed.
When the FSP_UGOP_EARLY_SIGN_OF_LIFE flag is set, coreboot is configured
to use the UPDs mentioned above to show a text message during the memory
training phase. This text message can be customized through the locale
text mechanism using the identifier memory_training_desc.
In addition, the newly introduced code records an extra event to
indicate when early Sign-Of-Life has been requested, to cover the Memory
Reference Code (MRC) training scenario. This event logging is crucial
for debugging and analyzing the boot process, especially in production
environments where it helps in pinpointing the exact stage where a boot
issue might occur.
TEST="Enabling FSP-M Sign-of-Life" message is present in the log upon
the first boot, and a message is displayed on the screen while the
FSP performs MRC training.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85454
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In the low battery poweroff scenario, the platform should halt after
issuing the poweroff command. This ensures that no further code
execution occurs, preventing potential issues.
Additionally, the do_low_battery_poweroff() function is marked with
__noreturn to indicate that it does not return. This is appropriate
because the platform will either power off or halt.
TEST=Able to compile google/fatcat.
Change-Id: Ieb77645283360b5731ca48b94551712b99109a1c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86578
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry.
It is annoying when searching for the wrong abbreviation in the spec so
fix it everywhere it occurs.
source: Intel 64 spec April 2022 and AMD64 spec April 2024.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I730235beea69b3720f080bbade083c2eeed26587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
HWRot (Hardware Root of trust) is not used, so we disable its clocks to
save power. This patch is a subitem of Vcore power consumption
improvement. The whole work improves SoC power consumption from 120mW to
90mW in suspend.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK & Suspend/Resume passed
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86553
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit `fb2c09d516` stopped the SSDT
containing TPM tables if PTT was not active, as at the time, the
table unconditionally reported the device present in the _STA
method.
Commit `d503ce1277` made the _STA to
return an accurate state, so now, the tables can always be
generated and Linux will report the presence correctly.
Change-Id: I594bf25a207b809c1ae2632eb1aea0d0fb6df35e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If CONFIG(CRB_TPM) is enabled but the TPM is inactive, and no other TPM
interface (SPI, I2C, Memory-Mapped) is configured, the function would
incorrectly fallback to generate a TPM2 table for FIFO mode.
This commit adds a check to ensure crb_tpm_is_active() is only
called if CONFIG(CRB_TPM) is enabled and no other TPM interface
is present. If the CRB TPM is inactive and no other TPMs are
available, the function now exits early to prevent generating
an invalid TPM2 table.
Test=boot `starlabs/starlite_adl` and check Linux doesn't probe for a
TPM when PTT is not active.
Change-Id: I153779aa1f3d84ffeb694543f9da1d09b120f98f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
List of changes -
1. Make GPP_B3 IRQ only pin.
2. Remove redundant GPE option from touchpad device.
BUG=b:397905085
TEST=Verified wake from S0ix using touchpad.
Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Manually confgiure the vGPIO's related to CNVi for USB Bluetooth
instead of UART.
Change-Id: I7d6007e40b2edbadeb5611f6cd67df0c1e6ee8a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86565
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO is not connected, so configure it accordingly.
Change-Id: I4b3421f1ab676599ffec6b2f46429ce937704e40
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86564
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace all occurrences of u8, u16, u32 and u64 with their respective
alternatives of uint8_t. There is no need to unnecessarily compress code
by using standard types aliases.
BUG=b:391874512
TEST=Compile cbmem
Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
It seems FSP will only automatically configure the vGPIO's for
CNVi Bluetooth if USB 2 Port 7 is used. On this board, USB 2
Port 9 is used, so manually confgiure the vGPIO's related to
CNVi for USB Bluetooth instead of UART.
Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard is marked IQ1X0MS, though it is also known as the MS-7988.
The Small Form Factor version was used for this port, though the Mini
Tower seems to use the exact same board. Other systems such as the
ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre
700-25ISH appear to use the same PCB with different configurations of
components.
All the code in this port was originally copied from the Asrock H110M
and then modified to match the actual configuration of the M900. The VBT
was extracted using `intelvbttool -l -v data.vbt` while running version
FWKTBFA of the vendor firmware.
Working:
- Boots to Linux with SeaBIOS 1.16.3
- Boots to Linux with EDK2 (MrChromebox uefipayload_202408)
- Display Ports
- VGA port
- PCIe slots
- Console over serial port
- Front and rear USB 3.0 ports and internal USB2.0 headers
- Front and rear audio jacks
- Internal speaker
- SATA ports 1-4 (5 and 6 are not populated on the M900)
- Hardware monitoring via nct6683 kernel module
- Gigabit Ethernet
- S3 suspend/resume
Unknown/untested:
- M.2 E-key slot
- Parallel port header
- PS/2 Mouse/Keyboard via KB_MS1 header
- TPM
Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB.
BUG=b:379008996
BRANCH=none
TEST=booted successfully
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86538
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move gpio_get_eint_reg() and gpio_calc_eint_pos_bit() to common code
to avoid redundant definitions for other platforms such as MT8189.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id21f627a49f730f3a0db786a148f81806aeba287
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the HAVE_ACPI_RESUME config option from the Google
Brya mainboard configuration. The Intel Alder Lake SoC does not support
S3 (ACPI sleep state) entry/exit, and attempting S3 validation could
lead to abnormal platform behavior. This change ensures that `_S3` is
not listed as a valid wake source in the DSDT (Differentiated System
Description Table) after booting to the OS.
BUG=b:337274309
TEST=Boot verfied google/trulo.
TEST=Veified that the _S3 name variable is not present in the DSDT ASL.
Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86422
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the vendorcode openSIL memory map code and move all common
calls that do not require any openSIL headers to the driver. Improve
the legibility of the logic to return memory hole type string.
Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need to know how many combo entries have been processed.
It will be checked in functions in later change.
Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85590
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up the code to make it more logical.
This is for later changes to reorder the PSP Level 1, Level 2, ISH and
BIOS tables.
TEST=Identical test on all AMD platform
Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84531
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For A/B recovery, it is better, even though it is not mandatory, to
put BIOS level 2 table next to its PSP level2. So the relative
addresses of BIOS table are the same. So all the data in B could be a
copy of A.
Identical binary test on all non A/B recovery platform.
Booting test on Majolica with A/B recovery enabled.
Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The current SMBIOS for fatcat is missing processor upgrade information.
This patch adds the missing value by enabling kconfig flag
CPU_INTEL_SOCKET_OTHER.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
Output of dmidecode:
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPU0
Type: Central Processor
Family: Pentium Pro
Manufacturer: GenuineIntel
ID: C0 06 0C 00 FF FB EB BF
Signature: Type 0, Family 6, Model 204, Stepping 0
Flags: ...
Version: Genuine Intel(R) 0000
Voltage: Unknown
External Clock: 100 MHz
Max Speed: 3200 MHz
Current Speed: 3000 MHz
Status: Populated, Enabled
- Upgrade: Unknown
+ Upgrade: Other
BUG=NONE
TEST=Boot and verified that SMBIOS processor upgrade value is correct.
Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Fix USB port assignments/descriptions to match actual topology.
TEST=build/boot Win11 on starlabs/starbook_adl_n. Verify ports
match assignmented in devicetree using USBTreeview.
Change-Id: If0b341f1c5f99b53df8fff69f8a58fa732adbbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Unselect LIBGFXINIT to bring these two variants inline with the
others.
Change-Id: If0fdc9ffd391f2710f252be7358d87644a77b36a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
According to the design, the SPI ROM will be replaced
with a 16MB size, so the Kconfig is modified to 16MB.
BUG=b:397372760
TEST=emerge-nissa coreboot and check rom size is 16MB
Change-Id: I3ef1aa2401d44259e4301f65e2ba0ac7b9418bbd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86501
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
