Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each jecht variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: I10e318e7bb6ea6ee3f4b0d5c210c4c7d639adce4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f069edb975
Original-Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19971
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524596
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each auron variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic677f49c4355da471c50b55afc2a6351d8e0f27d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c3c7a1dcb
Original-Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19970
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524595
Since dual-channel setups use same RAM/SPD for both channels,
populate spd_data[1] with same SPD data as spd_data[0],
allowing info for both channels to propogate into the
SBMIOS tables.
Clean up calculations using SPD length to avoid repetition.
Changes modeled after google/auron variants.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4f74548fd00577e1730c4535b8ea5c59b096f3ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cadd7c7ed3
Original-Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19981
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523980
sata_devslp_disable was set to work around some buggy SSD
firmware, but as it's disabled by default in both Linux and
Windows, no reason to disable at the firmware level when
many properly-functioning SSDs can take advantage of power
savings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f317e963dbc88a766be5da9e2266e328c4ed1ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a5c6201da
Original-Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19957
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523977
Fix for all Sandy-Bridge and Ivy-Bridge devices.
Remove unused option "hyper_threading".
Increase CMOS checksum range to cover all user adjustable settings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3d0eab9eb780aff5e132a96fe436cae212426c69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3de6d38642
Original-Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19955
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523976
This is to align with the SD_CD GpioInt setting in acpi
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: Id2c151cb8549e0c447c4a1494556f1cf6a55d0ac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8cb70914ca
Original-Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20001
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523975
The separate directory was the old way of handling variant boards.
Update bakersport_fsp to the new method. All of the other pieces
were already moved into bayleybay_fsp.
BUG=none
BRANCH=none
TEST=none
Change-Id: I43f64bde643de00db0eb4c0d165651732d33b333
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41807626e2
Original-Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19077
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/523971
Light sensor isn't used and ACPI already removed, so disable
I2C5 bus interface as well.
Disable I2C6 for devices without a touchscreen
BUG=none
BRANCH=none
TEST=none
Change-Id: I82dd1cfe7fc9f5635391431dd00b7bd67b8b916a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f848ed091e
Original-Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19956
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523968
Remove MONOTONIC_TIMER_MSR selection from mainboard
Konfigs, as it only does a reduntant selection of
HAVE_MONOTONIC_TIMER config, already selected under
skylake soc Kconfig.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaeecb8b10205ed68cad6890e42e6a5f1acf3c1b1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 051d6085e4
Original-Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20002
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523964
Update camera sensor detail to OV 13858
Also update i2c address of OV5670
BUG=None
TEST= Build & boot to ChromeOS. Check for both the camera detection.
Change-Id: Ia097ac7da4c6dd0ceb30e930e1bd7c76cb155adc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: e7cb29493d
Original-Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20021
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523582
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This board is almost identical to D510MO, the only differences are
some differences in populated connections, CPU with less L2 cache and
a 10/100 Realtek NIC.
The vendor uses the very same binary for both D510M0 and D410PT.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie5dab03be5bf216297431ef539248087b8a8bd2c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 80d55b3ef3
Original-Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20000
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/522712
BUG=b:62147763
Change-Id: I87e629a15de2f6882c1bf6f238931751db7515fd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3178bdc345
Original-Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19953
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521040
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each slippy variant has slightly different USB port config;
data for falco and leon to be added once available
BUG=none
BRANCH=none
TEST=none
Change-Id: I0bde090fa65671806c58e5ee23d605cdc689a28a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 39480c7204
Original-Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19967
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521039
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
All beltino variants use the exact same USB port layout.
BUG=none
BRANCH=none
TEST=none
Change-Id: I603fe9cacddb841592886724b260868323c95bb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1186915c1f
Original-Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19966
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521038
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9dac338bae16f7e8ef4b68561ab60009905712a0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c5bd8b359b
Original-Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19963
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521035
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Port 0 is connected to SD-card reader.
Don't mark it as hot-plugable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3f7e4bd05d2619564408514a873d847e44cef5c0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a703393612
Original-Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19928
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/521033
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
To unify the hwinfo handling along all Siemens MC boards the hwinfo
files have to be removed from the mainboard directory. They will be added
to cbfs in site-local/Makefile.inc.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9cad8d637947c76327ffe1b22152e4d524f02424
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7a3d6e1435
Original-Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19982
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/521032
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The prior used RTC PCF8523 is replaced with RX6110SA on this mainboard.
Switch to the new RTC in Kconfig and adapt devicetree to the new chip.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6aedee70a912bce4c5c1c651aa8d4c4363b0f632
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cd37fef2e1
Original-Change-Id: I7c4911191cae254900f9a958da42ecd18497484c
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19979
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/521031
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.
BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.
Change-Id: I3b2c10e68c6772453fbc16094e9d00d950d872b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 07a597feff
Original-Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19947
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521029
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of having the SMI handler power off the touchscreen on the
way into suspend add power resource controls to the ACPI device so
the power is managed by the kernel instead of the BIOS.
BUG=b:35581264
TEST=manual testing on Eve to ensure that the touchscreen is still
functional at boot and after suspend/resume, and that it does not
draw power in suspend.
Change-Id: Ic1dd4ed8faab367347a4150c415a5cd40adb25f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f124b88cfb
Original-Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19946
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521028
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifeb6b0b2a4417bdb13908ceb0aa4e382b40a91c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c25b2a18fa
Original-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19786
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521025
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Get rid of mainboard_io_trap_handler.
The only purpose is to enable tp-smapi, but is already done on all
boards in h8_enable, as of devicetree setting config0.
BUG=none
BRANCH=none
TEST=none
Change-Id: If248d0142568db0f89b18225335bd8f336c55570
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 8953d4a137
Original-Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19790
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/517937
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1ef87d18b30192be730805238df62ff81f130339
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd82edc388
Original-Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19915
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/517936
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
GPP_C2 is being used as strapping option, so
should not be set to NF. Signal was floating
previously, which can lead to an assertion of
smbalert#.
BUG=b:37681121, b:35775024
BRANCH=None
TEST=powerd_dbus_suspend and ensure stays in suspend
Change-Id: Ife5a3d8c442e3f29c2dc549b9f6887d526cbf8f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c96f757af1
Original-Change-Id: I68091206014621419b886b723a5681541be989bc
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19904
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517935
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.
BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.
Change-Id: Ibae8907f260b50eb0d1283f26294fb73e963d051
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 73108ded48
Original-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19829
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517925
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Should result in a tiny speed bump in raminit since those addresses
are not checked for present DIMMs.
Checked in schematics of both Thinkpad X60 and T60 and tested to
configure raminit correctly for all DIMMs populated on X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib52cde02578aa34de55be6e9b482ba47019b9809
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 000cc598cb
Original-Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19862
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/515864
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I355a6b7527743f863e1fa34d52bca28506975aa9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 36dafd88bc
Original-Change-Id: Ia44097f32f74ffd749219415984224ce33d9252b
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19816
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/515863
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Soraka uses OV 13858 sensor. Hence update the same.
BUG=none
BRANCH=none
TEST=none
Change-Id: If48f4c2411f2450f2d617b342c587ccf5675a51e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b25b2329a9
Original-Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19639
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD),
it displays wrong part number during boot in coreboot logs.
So correct part number info within the SPD.
TEST= Build for Soraka & make sure part number is rightly printed.
Change-Id: I6ab2b81223364c7e48e9d64e080f459c27843d09
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1d407cceaf
Original-Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19692
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/514190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The SoC code was never completed. It's just a skeleton that gets
in the way of refactoring other code. Likewise, the mainboard was
never completed either. Just remove them both.
BUG=none
BRANCH=none
TEST=none
Change-Id: I19d42549463e9726bcd4bcd119634733a933e184
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 250715eb2f
Original-Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19823
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/513957
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I781280dad7477dd55788db2e487e20f4ec911b33
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 10326ba889
Original-Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19801
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510773
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
All those boards do not have a serial port.
Don't attempt to decode the COMA/COMB IO range.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14fd3107b5fcf74c04d319b71971058e4f39736c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 93eac6a89d
Original-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19571
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibed8577d19b6490545019d6bf142230c82fb181c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ac27d3688a
Original-Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19570
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510768
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ec6e0dbb1006be79b9a9412d5a60eb1c4b4590d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3db82be764
Original-Change-Id: I77aabf98ea48c6e8bdbe322f89666935f59a289a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19760
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/510765
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b89a0b86082e5b57a53c5c7c6fd9fe0c9db6167
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1222162d12
Original-Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/510762
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=b:37712455
Change-Id: Ia5aa6665db0f8199de8d2cf363272d7e2b676363
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 365d97e938
Original-Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19766
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509526
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix SPD as per the vendor-provided data.
BUG=b:37712790
Change-Id: Id2054c54ec61c7bd3e9161c70506f45d31fd36d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 77be7339cd
Original-Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19749
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509525
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested and working:
* HDD LED
* Booting GNU Linux 4.9 from HDD using SeaBios
* Booting GNU Linux 4.9 from USB using SeaBios
* Native GFX init
* All Fn function keys
* Speakers
* PCIe Wifi
* Camera
* WWAN
* Fan (Dynamic Thermal Managment)
* Flashing using internal programmer
* Dual memory DIMMs running at up to DDR3-1866
* AC events
* Touchpad, trackball and keyboard
* USB3 ports running at SuperSpeed
* Ethernet
* Headphone jack
* Speaker mute
* Microphone mute
* Volume keys
* Fingerprint sensor
* Lid switch
* Thinklight
* TPM (disable SeaBios CONFIG_TCGBIOS)
* CMOS options:
** power_on_after_fail
** reboot_counter
** boot_option
** gfx_uma_size
** usb_always_on
Untested:
* Booting Windows
* Hybrid graphics
* Docking station
* VGA
Broken:
* Wifi LED is always on
BUG=none
BRANCH=none
TEST=none
Change-Id: I8e9aa289a838691ce6edcddeb42cb4d1a865a609
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 714baa119b
Original-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18011
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/509516
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Id27b75d20f71bdb6c532796944e62aea79d9174d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aeae34ffa4
Original-Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19551
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509515
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This reverts commit 6434755b96.
Revert the revert to get the touchpad ID ready for
the new touchpad firmware again.
BUG=b:35581264
BRANCH=none
TEST=none
Change-Id: I0c70f2c7c844d9199b9098783c24a6a0460263cc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506785
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
TEST=Boot from scarlet, and mipi panel works
Change-Id: I28ae05e1d3681a6012da80cf2e2dae196110559c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 36b09b8a6c
Original-Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19700
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508774
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Program eMMC DLL settings for mc_apl1 mainboard, after that system can
boot up with eMMC successfully.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ife34e1b5079eca8e51f2270439dbe05d613ed688
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c7ccb6b29f
Original-Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19712
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/508771
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The mainboard siemens/mc_apl1 uses an external I/O port for console
output. For this reason we need to activate the 8250 LPC UART.
BUG=none
BRANCH=none
TEST=none
Change-Id: I32e68e06a64308bf56010ce2e8e48ba42fd788b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ae10ec6239
Original-Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19694
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This device is no longer directly connected to the SOC so it
does not need to be enabled in coreboot.
BUG=b:35648259
TEST=build and boot on Eve
Change-Id: I5c13d993a2f37a023208fba2b745b70e9db9e310
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: c5eab98e78
Original-Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19728
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/507638
The touchpad frequency was still slightly above 400kHz so tweak
the timing values manually to get under the spec limit.
BUG=b:35583133
TEST=verified the bus frequency with a scope to be < 400kHz
Change-Id: I07b171ebe912bf603049656e48beeeabdd56fef6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 4f7d536ed3
Original-Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19727
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/507637
