UPSTREAM: mb/lenovo/*/romstage: Remove COM IO port
All those boards do not have a serial port.
Don't attempt to decode the COMA/COMB IO range.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14fd3107b5fcf74c04d319b71971058e4f39736c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 93eac6a89d
Original-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19571
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
parent
9fd24bd2b3
commit
913e573631
10 changed files with 9 additions and 35 deletions
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@ -25,12 +25,11 @@
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void pch_enable_lpc(void)
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{
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
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}
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void rcba_config(void)
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@ -42,7 +42,6 @@ void pch_enable_lpc(void)
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);
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/* Memory map KB9012 EC registers */
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@ -24,15 +24,12 @@ void pch_enable_lpc(void)
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/* EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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@ -27,15 +27,12 @@ void pch_enable_lpc(void)
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/* EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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@ -27,15 +27,12 @@ void pch_enable_lpc(void)
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/* EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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@ -41,15 +41,12 @@ void pch_enable_lpc(void)
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/* T520 EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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@ -28,15 +28,12 @@ void pch_enable_lpc(void)
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/* X230 EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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@ -42,15 +42,12 @@ void pch_enable_lpc(void)
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/* X230 EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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@ -38,15 +38,12 @@ void pch_enable_lpc(void)
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/* X230 EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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@ -41,15 +41,12 @@ void pch_enable_lpc(void)
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/* X230 EC Decode Range Port60/64, Port62/66 */
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/* Enable EC, PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
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COMA_LPC_EN);
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CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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