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UPSTREAM: mb/lenovo/*60: Remove not existing DIMMs from SPD map

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Should result in a tiny speed bump in raminit since those addresses
are not checked for present DIMMs.

Checked in schematics of both Thinkpad X60 and T60 and tested to
configure raminit correctly for all DIMMs populated on X60.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ib52cde02578aa34de55be6e9b482ba47019b9809
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 000cc598cb
Original-Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19862
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/515864
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-05-24 10:57:13 +02:00 • committed by chrome-bot
commit d855ced429
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/lenovo/t60/romstage.c
View file

@ -172,7 +172,7 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
int dock_err;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
timestamp_init(get_initial_timestamp());

2
src/mainboard/lenovo/x60/romstage.c
View file

@ -171,7 +171,7 @@ static void early_ich7_init(void)
void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
timestamp_init(get_initial_timestamp());