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UPSTREAM: mb/gigabyte/ga-g41m-es2l: Enable IO decode range for LPT and FDD

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BUG=none
BRANCH=none
TEST=none

Change-Id: I3ec6e0dbb1006be79b9a9412d5a60eb1c4b4590d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3db82be764
Original-Change-Id: I77aabf98ea48c6e8bdbe322f89666935f59a289a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19760
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/510765
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-05-18 13:23:39 +02:00 • committed by chrome-bot
commit 02783f0dab
1 changed files with 2 additions and 1 deletions
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src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
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@ -123,7 +123,8 @@ static void ich7_enable_lpc(void)
/* Decode range */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN
| LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);