Add GENERIC_UDELAY Kconfig option so that a generic
udelay() implementation is provided utilizing the
monotonic timer. That way each board/chipset doesn't
need to duplicate the same udelay(). Additionally,
assume that GENERIC_UDELAY implies init_timer()
is not required.
BUG=None
BRANCH=None
TEST=Built nyan, ryu, and rambi. May need help testing.
Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219719
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of open coding monotonic timer usage,
use the stopwatch API.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219716
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=None, but similar usage tested on tegra132.
Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219713
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=Built, but similar usage tested on tegra132.
Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219712
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
It causes fan top speed due to this bug + our board-specific workaround,
and causes invalid temperature sensor readings.
Therefore, re-configure the register "External Temperature Sensor Host
Control Register" to terminate processes when this issue happens.
BUG=chromium:402204
TEST=ran suspend_stress_test 500 times
Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219445
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Instead of open coding the monotonic timers use the stopwatch
abstraction.
BUG=None
BRANCH=None
TEST=Booted and noted timings work as expected. Built with software_i2c
and no compilation failures.
Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219495
Reviewed-by: Julius Werner <jwerner@chromium.org>
Simplify the timed operations by using the stopwatch API.
BUG=None
BRANCH=None
TEST=Built and booted to kernel. Analyzed logs. Output as expected.
Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219494
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Most Baytrail based devices MMIO registers are reported in ACPI
space and the device's PCI config space is disabled. The PCI config
space is required for many "legacy" OSs that don't have the ACPI
driver loading mechanism. Depthcharge signals the legacy boot
path via the SMI 0xCC and the coreboot SMI handler can switch the
device specific registers to re-enable PCI config space.
BUG=chrome-os-partner:30836
BRANCH=None
TEST=Build and boot Rambi SeaBIOS.
Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/219801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Tested-by: Mike Loptien <mike.loptien@se-eng.com>
Simplify the SPI timeout by using the stopwatch.
BUG=None
BRANCH=None
TEST=Built nyan. Confirmed stopwatch works independently.
Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219493
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
There's a lot of places where expiration and running time are
open coded. Allow for those places to be simplified by adding
a stopwatch construct. The stopwatch can have an expiration or
just be used to accumulate time.
BUG=None
TEST=Built and verified API works as expected by using implementation.
Change-Id: I53604900fea7d46beeccc17f1dc7900d5f28518b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219492
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
OBFF: Disable it by clear bit fields in that W/O register.
RO: Enable Relaxed Ordering from each enabled Root Port.
Linker Arbiter: Set it to recommeded setting.
BUG=None
TEST=Build a image and check the setting are applied correctly on
Samub.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c
Reviewed-on: https://chromium-review.googlesource.com/219993
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
Extended PCIe Capability and Advanced Error Report locates at
offset 0x100 is W/O, and the subsequent write following the 1st
write to the register takes no effect.
BUG=chrome-os-partner:31424.
TEST=Build a image and check the programming value is correct on
Samus.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db
Reviewed-on: https://chromium-review.googlesource.com/219985
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Auron/Peppy use GPIO 12 and GPIO 25 as wake up pins. GPIO_OWN,
GPIO_ROUTE, GPnCONFIG registers are setup if _DSW methods
are available.
Example capture after GPIO 12 and 25 are enabled for wake up:
GPIO Registers: GPIO_OWN_0 3dfbea0f GPIO_ROUTE_0 00000000
GPIO Registers: GPnCONFIGA_12 4000000d GPnCONFIGB_12 00000000
GPIO Registers: GPnCONFIGA_25 4000000d GPnCONFIGB_25 00000000
As Duncan suggested, I moved _PRW and _DSW to respective trackpad
and touch screen devices, and wake up worked with latest Chrome
image R39.6301.
Trackpad wake up is automatically enabled after boot. But touch
screen wake up is not enabled by powerd on boot.
BUG=chrome-os-partner:32047
TEST=check if trackpad can wake up board
Change-Id: Idd1e93dee8678044a6756cf36e8fdf4d27cd9676
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219906
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Configure IOSF Port and Grant Count.
BUG=None
TEST=Build coreoot image and run on Samus to confirm the setting
is properly applied.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3
Reviewed-on: https://chromium-review.googlesource.com/219523
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
BUG=chrome-os-partner:32015
BRANCH=None
TEST=successfully suspend/resume on Rush/Ryu
Signed-off-by: Yen Lin <yelin@nvidia.com>
Change-Id: I11cca0a8f5e7a36c1fff690c8070c74706348949
Reviewed-on: https://chromium-review.googlesource.com/214580
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Yen Lin <yelin@nvidia.com>
Tested-by: Yen Lin <yelin@nvidia.com>
Copied dlaurie's entry from Rambi board. On Auron/Peppy
board, IRQ is hooked to GPIO 51. Based on table 5-36, this
is PIRQT. Then based on table 5-12, this is IRQ #35.
Thanks to Duncan for the pointer!
BUG=chrome-os-partner:32237
TEST=check if ALS is found by the kernel
Change-Id: I97bd932b48a6512632ee747715926a5761a7aeca
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219631
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
this change makes the bootblock jump to the verstage when VBOOT2_VERIFY_FIRMWARE
is set.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I868b2c1888a55fd181e10856fd0f58d01086355c
Reviewed-on: https://chromium-review.googlesource.com/219626
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this change makes prevent execution from falling through to unverified
code when hard_reset is not implemented. it also includes a few touch-ups.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I9b02ab766172a62c98b434c29f310bc4a44f342d
Reviewed-on: https://chromium-review.googlesource.com/219625
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
There's no need to add DMA ranges for these boards as
that memory is allocated within dpethcharge now. Additionally,
the DRAM_DMA_* Kconfig options were removed resulting in 0
values.
BUG=None
TEST=Built rush and ryu.
BRANCH=None
Change-Id: I52bb8f760a56226c75611f7981570a44d56f242e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219710
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
With VPD blob of certain format, CBFS cache on storm proves to be not
large enough. This patch makes it bigger, it is still well above the
area preserved for the NSS.
BUG=chrome-os-partner:32152
TEST=the system now boots with the VPD it used to fail booting.
Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219572
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pass MAC addresses found in coreboot table into lib_sysinfo.
BUG=chrome-os-partner:32152
TEST=with all changes in place MAC addresses are properly inserted
into the kernel device tree.
Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219444
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Chrome OS devices firmware usually includes an area called VPD (Vital
Product Data). VPD is a blob of a certain structure, in particular
containing freely defined variable size fields. A field is a tuple of
the field name and field contents.
MAC addresses of the interfaces are stored in VPD as well. Field names
are in the form of 'ethernet_macN', where N is the zero based
interface number.
This patch retrieves the MAC address(es) from the VPD and populates
them in the coreboot table so that they become available to the
bootloader.
BUG=chrome-os-partner:32152, chromium:417117
TEST=with this and other patches in place the storm device tree shows
up with MAC addresses properly initialized.
Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coreboot generic CBFS media API does not support
multiple media access instances, but it should.
With this fix the CBFS context (memory cache for
SPI accesses) is shared among all open media access
streams. A better memory management scheme might be
required, but for now this fix allows to support
booting deptcharge and accessing VPD through two
independent CBFS media streams.
BUG=chrome-os-partner:32152
TEST=no exception is thrown when the second stream
is opened
Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219441
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Flashmap offset needs to be defined through
configuration option. This definition must match
the FMAP location defined the appropriate device
tree in the deptcharge repository.
BUG=chrome-os-partner:32152
TEST=attempts to look up VPD in flash map do not
fail anymore
Change-Id: I474f0c4854fc264bcae8eb27fbd43966a381aa91
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219440
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cleanup of functions to write to clk_enb and rst_dev registers and addition of
clock_disable and clock_set_reset functions to provide a complete API for
updating the registers.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles
successfully on rush
Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/219191
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Since PSCI dynamically determines which EL to transition
to based on SCR_EL3 there's no need to provide that
information.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel with MP.
Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218924
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The PSCI functionality initially includes CPU_ON and CPU_OFF
functions. Upon entering secmon the if the parameters are non-NULL
then a PSCI CPU_ON action is done for the current CPU.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Booted kernel with PSCI support. Brought up all CPUS in kernel
using PSCI. Turned CPUs on and off.
Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218923
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
If an exception is taken that the secmon won't return
to there needs to be way to reset that cpu's state
w.r.t. stack usage. Therefore, provide secmon_trampoline
which will reinitialize the exception stack and SP_EL0
and start executing with SP_EL0 like the initial state
of the secmon entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also tested when is PSCI
is employed in the kernel.
Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218922
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Two things:
1. Not returning once setting the return state.
2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x))
With these 2 changes arguments and results are being processed
correctly.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and brought up SMP using PSCI.
Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218847
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=None
TEST=Modify settings, build and update the image to Samus and
check the settings are applied to Registers.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
Reviewed-on: https://chromium-review.googlesource.com/219073
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Do the absolute minimum needed to allow the DPAUX mux ctl write
for I2C6. This leaves HOST1X off (reset and clock disabled) to
avoid a conflict with any kernel display driver init.
I2C6 init/enable will be moved to ramstage in the next CL.
BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/218900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to process PSCI commands SMC instructions need to be
serviced. Provide a simple way for users of SMC to register their
handlers by function.
The SMC layer hooks into the exception processing, however it only
processes AARCH64 SMC calls. All others are ignored.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Added nop smc call to depthcharge. SMC handled and continue booting
to kernel.
Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218846
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
The exception vectors were not reinitialized in secmon yet.
Add that as well as the split BSP vs non-BSP path. In doing
so bring in the cpu.c semantics for determining bsp at runtime.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also noted only one CPU
printing messages.
Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218845
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
mosys will use this field to identify system
BRANCH=none
BUG=chromium:359155
TEST=build ok, make sure mosys can be executed on Auron
use dmidecode to check data is written correctly
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I597e78251250e26c02b13636e9a220a150dfa6ce
Reviewed-on: https://chromium-review.googlesource.com/217493
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
It's helpful to differentiate the startup paths for
the BSP and the non-BSP. Therefore have c_entry
be an 2 element array of function pointers. The
non-BSP paths have an entry point one instruction after
stage/module entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218844
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built secmon which had this type of relocation.
Change-Id: If170d9e270daf3153e92d16c06516915c727e930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218843
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The cpu.c contains some helpful construts as well as ramstage
devicetree handling. Split the 2 pieces so that cpu.c can be
reused in secmon.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted.
Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218842
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to not break FAFT, and to have a quicker recovery
mode boot, reboot the PD controller into RO image in romstage.
This is done before the EC since rebooting the EC into RO will
also reboot the host.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot samus EVT into recovery with 'dut-control power_state:rec'
and ensure that the PD controller is rebooted to RO in romstage.
Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
currently, if the cache size is, for example, 4096 byte, mapping 4096 byte data
fails due to the overly strict check. this change allows cbfs_simple_buffer_map
to use all the cache space to the last byte.
BUG=None
TEST=Booted Nyan Blaze.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I0797b5010afd7316fdec605784e8f48e2d62c37f
Reviewed-on: https://chromium-review.googlesource.com/218883
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coreboot needs to be able to reboot the PD controller into RO
image in recovery mode early in the boot process in order to
avoid a lengthy recovery mode boot if it is only done at vboot
software sync time.
In order to do this a new device index field is added to the
command structure which must be initaalized to zero for all EC
transactions.
This early init and image check code is only used in romstage so
include it in the __PRE_RAM__ block.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=build and boot on samus EVT in recovery mode and see that
the PD is rebooted to RO mode early in the boot.
Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to talk to the PD controller with a passthru command
coreboot needs to be able to use v3 commands.
The command version is automatically detected based on the
advertized flags from the EC.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot on samus EVT
Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
