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Hung-Te Lin 2d3ec06ec3 tegra124: Run bootblock and ROM stage out of DRAM. 
To allow doing DRAM initialization in ROM stage instead of BootROM, we need to
move bootblock and ROM stage base address into iRAM, also the stack and CBFS
cache area just like TTB.

BUG=none
TEST=Boots on Nyan without problem.

Change-Id: I459faef5eb0f75561089dafbb111ae83729c3a29
Reviewed-on: https://chromium-review.googlesource.com/179822
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
2013-12-13 09:23:47 +00:00
..
arch exynos: Install the BL1 and set the checksum in the Makefile. 2013-12-10 03:26:39 +00:00
console ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
cpu x86: Add SMM helper functions to MP infrastructure 2013-10-23 04:08:19 +00:00
device pnp: Allow setting of misc register 0xfa in device tree 2013-11-08 00:52:45 +00:00
drivers tpm: Clean up I2C TPM driver 2013-11-11 23:47:09 +00:00
ec baytrail: Basic DPTF framework 2013-12-11 19:50:19 +00:00
include cbmem: Export ACPI GNVS cbmem pointer in coreboot table 2013-12-13 03:55:46 +00:00
lib cbmem: Export ACPI GNVS cbmem pointer in coreboot table 2013-12-13 03:55:46 +00:00
mainboard tegra124: norrin: fix display issue 2013-12-13 02:44:27 +00:00
northbridge haswell: Report x32 memory as "x8 or x32" 2013-10-23 21:27:19 +00:00
soc tegra124: Run bootblock and ROM stage out of DRAM. 2013-12-13 09:23:47 +00:00
southbridge lynxpoint: Add SATA DEVSLP disable option 2013-11-15 04:58:50 +00:00
superio pnp: Allow setting of misc register 0xfa in device tree 2013-11-08 00:52:45 +00:00
vendorcode baytrail: Add support for LPSS and SCC devices in ACPI mode 2013-12-11 19:50:27 +00:00
Kconfig Fix the reg_script stuff to not be used in ARM builds and not break them. 2013-11-02 01:07:13 +00:00