ARM: Generalize armv7 as arm.

There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.

BUG=chrome-os-partner:23009
TEST=Built libpayload and coreboot for link, pit and nyan. Booted into the
bootblock on nyan.
BRANCH=None

Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>

Makefile

@@ -113,14 +113,14 @@ else
 
 include $(HAVE_DOTCONFIG)
 
-ARCHDIR-$(CONFIG_ARCH_ARMV7)   := armv7
+ARCHDIR-$(CONFIG_ARCH_ARM)   := arm
 ARCHDIR-$(CONFIG_ARCH_X86)     := x86
 
 ARCH-y := $(ARCHDIR-y)
 
 # If architecture folder name is different from GCC binutils architecture name,
 # override here.
-ARCH-$(CONFIG_ARCH_ARMV7)   := armv7
+ARCH-$(CONFIG_ARCH_ARM)   := arm
 ARCH-$(CONFIG_ARCH_X86)     := i386
 
 ifneq ($(INNER_SCANBUILD),y)

payloads/libpayload/Config.in

@@ -67,10 +67,10 @@ choice
         prompt "Target Architecture"
         default ARCH_X86
 
-config ARCH_ARMV7
-        bool "ARMv7"
+config ARCH_ARM
+        bool "ARM"
         help
-          Support the x86 architecture
+          Support the ARM architecture
 
 config ARCH_X86
         bool "x86"

payloads/libpayload/Makefile

@@ -91,14 +91,14 @@ include util/kconfig/Makefile
 
 include $(HAVE_DOTCONFIG)
 
-ARCHDIR-$(CONFIG_LP_ARCH_ARMV7)   := armv7
+ARCHDIR-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCHDIR-$(CONFIG_LP_ARCH_X86)     := x86
 
 ARCH-y := $(ARCHDIR-y)
 
 # If architecture folder name is different from GCC binutils architecture name,
 # override here.
-ARCH-$(CONFIG_LP_ARCH_ARMV7)   := armv7
+ARCH-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCH-$(CONFIG_LP_ARCH_X86)     := i386
 
 CC := $(CC_$(ARCH-y))

payloads/libpayload/Makefile.inc

@@ -31,7 +31,7 @@
 
 export KERNELVERSION      := 0.2.0
 
-ARCHDIR-$(CONFIG_LP_ARCH_ARMV7)   := armv7
+ARCHDIR-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCHDIR-$(CONFIG_LP_ARCH_X86)     := x86
 DESTDIR ?= install
 

payloads/libpayload/arch/Config.in

@@ -27,5 +27,5 @@
 ## SUCH DAMAGE.
 ##
 
-source "arch/armv7/Config.in"
+source "arch/arm/Config.in"
 source "arch/x86/Config.in"

payloads/libpayload/arch/arm/Config.in

@@ -27,7 +27,7 @@
 ## SUCH DAMAGE.
 ##
 
-if ARCH_ARMV7
+if ARCH_ARM
 
 config ARCH_SPECIFIC_OPTIONS # dummy
 	def_bool y

payloads/libpayload/arch/arm/cache.c

@@ -276,7 +276,7 @@ void dcache_mmu_enable(void)
 	write_sctlr(sctlr);
 }
 
-void armv7_invalidate_caches(void)
+void arm_invalidate_caches(void)
 {
 	uint32_t clidr;
 	int level;

payloads/libpayload/arch/arm/timer.c

@@ -28,8 +28,8 @@
  */
 
 /**
- * @file armv7/timer.c
- * ARMv7 specific timer routines
+ * @file arm/timer.c
+ * ARM specific timer routines
  */
 
 #include <libpayload.h>

payloads/libpayload/bin/lpgcc

@@ -107,9 +107,9 @@ while [ $# -gt 0 ]; do
 	shift
 done
 
-if [ "$CONFIG_LP_ARCH_ARMV7" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/armv7
-  _ARCHLIBDIR=$_LIBDIR/armv7
+if [ "$CONFIG_LP_ARCH_ARM" = "y" ]; then
+  _ARCHINCDIR=$_INCDIR/arm
+  _ARCHLIBDIR=$_LIBDIR/arm
   _ARCHEXTRA=""
 fi
 

payloads/libpayload/configs/config.bayleybay

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set
 # CONFIG_LP_MULTIBOOT is not set

payloads/libpayload/configs/config.beltino

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.bolt

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.daisy

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-CONFIG_LP_ARCH_ARMV7=y
+CONFIG_LP_ARCH_ARM=y
 # CONFIG_LP_ARCH_POWERPC is not set
 # CONFIG_LP_ARCH_X86 is not set
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.falco

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.fox_baskingridge

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.fox_wtm2

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.link

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.lumpy

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.nyan

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-CONFIG_LP_ARCH_ARMV7=y
+CONFIG_LP_ARCH_ARM=y
 # CONFIG_LP_ARCH_POWERPC is not set
 # CONFIG_LP_ARCH_X86 is not set
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.peach_kirby

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-CONFIG_LP_ARCH_ARMV7=y
+CONFIG_LP_ARCH_ARM=y
 # CONFIG_LP_ARCH_POWERPC is not set
 # CONFIG_LP_ARCH_X86 is not set
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.peach_pit

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-CONFIG_LP_ARCH_ARMV7=y
+CONFIG_LP_ARCH_ARM=y
 # CONFIG_LP_ARCH_POWERPC is not set
 # CONFIG_LP_ARCH_X86 is not set
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.peppy

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/config.slippy

@@ -15,7 +15,7 @@ CONFIG_LP_CHROMEOS=y
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/configs/defconfig

@@ -15,7 +15,7 @@
 #
 # Architecture Options
 #
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
 # CONFIG_LP_ARCH_POWERPC is not set
 CONFIG_LP_ARCH_X86=y
 # CONFIG_LP_MEMMAP_RAM_ONLY is not set

payloads/libpayload/include/arm/arch/cache.h

@@ -26,11 +26,11 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * cache.h: Cache maintenance API for ARMv7
+ * cache.h: Cache maintenance API for ARM
  */
 
-#ifndef ARMV7_CACHE_H
-#define ARMV7_CACHE_H
+#ifndef ARM_CACHE_H
+#define ARM_CACHE_H
 
 #include <stddef.h>
 #include <stdint.h>
@@ -320,8 +320,8 @@ void tlb_invalidate_all(void);
  * Generalized setup/init functions
  */
 
-/* invalidate all caches on ARMv7 */
-void armv7_invalidate_caches(void);
+/* invalidate all caches on ARM */
+void arm_invalidate_caches(void);
 
 /* mmu initialization (set page table address, set permissions, etc) */
 void mmu_init(void);
@@ -338,4 +338,4 @@ void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
 void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
 						enum dcache_policy policy);
 
-#endif /* ARMV7_CACHE_H */
+#endif /* ARM_CACHE_H */

payloads/libpayload/include/cbfs_core.h

@@ -106,7 +106,7 @@ struct cbfs_header {
  */
 #define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
 #define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARMV7    0x00000010
+#define CBFS_ARCHITECTURE_ARM      0x00000010
 
 /** This is a component header - every entry in the CBFS
     will have this header.

payloads/libpayload/util/xcompile/xcompile

@@ -106,7 +106,7 @@ detect_special_flags() {
 		CFLAGS="$CFLAGS -Wl,--build-id=none"
 
 	case "$architecture" in
-		armv7 )
+		arm )
 			# testcc "$CC" "$CFLAGS -mcpu=cortex-a9" &&
 			#	CFLAGS="$CFLAGS -mcpu=cortex-a9"
 			;;
@@ -135,13 +135,13 @@ touch "$TMPFILE"
 trap clean_up EXIT
 
 # Architecture definition
-SUPPORTED_ARCHITECTURE="x86 armv7"
+SUPPORTED_ARCHITECTURE="x86 arm"
 
 # ARM Architecture
-TARCH_armv7="armv7"
-TBFDARCH_armv7="littlearm"
-TCLIST_armv7="armv7a"
-TWIDTH_armv7="32"
+TARCH_arm="arm"
+TBFDARCH_arm="littlearm"
+TCLIST_arm="armv7a"
+TWIDTH_arm="32"
 
 # X86 Architecture
 TARCH_x86="i386"

payloads/tianocoreboot/libpayload.config

@@ -15,7 +15,7 @@
 #
 # Architecture Options
 #
-# CONFIG_ARCH_ARMV7 is not set
+# CONFIG_ARCH_ARM is not set
 # CONFIG_ARCH_POWERPC is not set
 CONFIG_ARCH_X86=y
 # CONFIG_MEMMAP_RAM_ONLY is not set

src/Kconfig

@@ -222,7 +222,7 @@ config ARCH_X86
 	default n
 	select PCI
 
-config ARCH_ARMV7
+config ARCH_ARM
 	bool
 	default n
 
@@ -232,8 +232,8 @@ if ARCH_X86
 source src/arch/x86/Kconfig
 endif
 
-if ARCH_ARMV7
-source src/arch/armv7/Kconfig
+if ARCH_ARM
+source src/arch/arm/Kconfig
 endif
 
 config HAVE_ARCH_MEMSET
@@ -275,7 +275,7 @@ config TPM
 	bool
 	default n
 	select LPC_TPM if ARCH_X86
-	select I2C_TPM if ARCH_ARMV7
+	select I2C_TPM if ARCH_ARM
 	help
 	  Enable this option to enable TPM support in coreboot.
 
@@ -303,7 +303,7 @@ source src/console/Kconfig
 config HAVE_UART_IO_MAPPED
 	bool
 	default y if ARCH_X86
-	default n if ARCH_ARMV7
+	default n if ARCH_ARM
 
 config HAVE_UART_MEMORY_MAPPED
 	bool

src/arch/arm/Kconfig

@@ -1,4 +1,4 @@
-menu "Architecture (armv7)"
+menu "Architecture (arm)"
 
 
 config ARM_ARCH_OPTIONS

src/arch/arm/Makefile.inc

@@ -38,7 +38,7 @@ ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y)
 bootblock-y += bootblock.S
 endif
 bootblock-y += id.S
-$(obj)/arch/armv7/id.bootblock.o: $(obj)/build.h
+$(obj)/arch/arm/id.bootblock.o: $(obj)/build.h
 bootblock-$(CONFIG_ARM_BOOTBLOCK_SIMPLE) += bootblock_simple.c
 bootblock-$(CONFIG_ARM_BOOTBLOCK_NORMAL) += bootblock_normal.c
 
@@ -79,7 +79,7 @@ rmodules-y += memcpy.S
 rmodules-y += memmove.S
 rmodules-y += eabi_compat.c
 
-VBOOT_STUB_DEPS += $(obj)/arch/armv7/eabi_compat.rmodules.o
+VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules.o
 
 romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -87,7 +87,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 ################################################################################
-# armv7 specific tools
+# arm specific tools
 
 ################################################################################
 # Common recipes for all stages
@@ -134,7 +134,7 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
 # TODO Change -b to Kconfig variable.
 $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
-	$(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
+	$(CBFSTOOL) $@.tmp create -m arm -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
 		-B $(objcbfs)/bootblock.bin -a 64 \
 		-b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \
 		-H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \
@@ -173,34 +173,34 @@ endif
 ################################################################################
 # Build the bootblock
 
-$(objcbfs)/bootblock.debug: $(src)/arch/armv7/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h
+$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -m armelf_linux_eabi -static -o $@ -L$(obj) $< -T $(src)/arch/armv7/bootblock.ld
+	$(LD) -m armelf_linux_eabi -static -o $@ -L$(obj) $< -T $(src)/arch/arm/bootblock.ld
 else
-	$(CC) $(CFLAGS) -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(src)/arch/armv7/bootblock.ld -Wl,--start-group $(bootblock-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
+	$(CC) $(CFLAGS) -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
 endif
 
 ################################################################################
 # Build the romstage
 
-$(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/armv7/romstage.ld $(obj)/ldoptions
+$(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm/romstage.ld $(obj)/ldoptions
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/armv7/romstage.ld
+	$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld
 else
-	$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
+	$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
 endif
 
 ################################################################################
 # Build the ramstage
 
-$(objcbfs)/coreboot_ram.debug: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $(src)/arch/armv7/coreboot_ram.ld $(obj)/ldoptions
+$(objcbfs)/coreboot_ram.debug: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $(src)/arch/arm/coreboot_ram.ld $(obj)/ldoptions
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -m -m armelf_linux_eabi -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(src)/arch/armv7/coreboot_ram.ld
+	$(LD) -m -m armelf_linux_eabi -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(src)/arch/arm/coreboot_ram.ld
 else
-	$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group -T $(src)/arch/armv7/coreboot_ram.ld
+	$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group -T $(src)/arch/arm/coreboot_ram.ld
 endif
 
 ################################################################################

src/arch/arm/bootblock.S

@@ -1,5 +1,5 @@
 /*
- * Early initialization code for ARMv7 architecture.
+ * Early initialization code for ARM architecture.
  *
  * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
  * U-Boot, which itself got the file from armboot.

src/arch/arm/bootblock_simple.c

@@ -38,7 +38,7 @@ void main(void)
 	sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
 	write_sctlr(sctlr);
 
-	armv7_invalidate_caches();
+	arm_invalidate_caches();
 
 	/*
 	 * Re-enable icache and branch prediction. MMU and dcache will be

src/arch/arm/cache.c

@@ -276,7 +276,7 @@ void dcache_mmu_enable(void)
 	write_sctlr(sctlr);
 }
 
-void armv7_invalidate_caches(void)
+void arm_invalidate_caches(void)
 {
 	uint32_t clidr;
 	int level;

src/arch/arm/coreboot_ram.ld

@@ -33,7 +33,7 @@ SECTIONS
 	.text : {
 		_text = .;
 		_start = .;
-		*(.text.stage_entry.armv7);
+		*(.text.stage_entry.arm);
 		*(.text);
 		*(.text.*);
 		. = ALIGN(16);

src/arch/arm/include/arch/cache.h

@@ -26,11 +26,11 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * cache.h: Cache maintenance API for ARMv7
+ * cache.h: Cache maintenance API for ARM
  */
 
-#ifndef ARMV7_CACHE_H
-#define ARMV7_CACHE_H
+#ifndef ARM_CACHE_H
+#define ARM_CACHE_H
 
 #include <config.h>
 #include <stddef.h>
@@ -327,8 +327,8 @@ void tlb_invalidate_all(void);
  * Generalized setup/init functions
  */
 
-/* invalidate all caches on ARMv7 */
-void armv7_invalidate_caches(void);
+/* invalidate all caches on ARM */
+void arm_invalidate_caches(void);
 
 /* mmu initialization (set page table address, set permissions, etc) */
 void mmu_init(void);
@@ -345,4 +345,4 @@ void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
 void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
 						enum dcache_policy policy);
 
-#endif /* ARMV7_CACHE_H */
+#endif /* ARM_CACHE_H */

src/arch/arm/include/arch/pci_ops.h

@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef ARCH_ARMV7_PCI_OPS_H
-#define ARCH_ARMV7_PCI_OPS_H
+#ifndef ARCH_ARM_PCI_OPS_H
+#define ARCH_ARM_PCI_OPS_H
 
 static inline const struct pci_bus_operations *pci_config_default(void)
 {

src/arch/arm/include/arch/stages.h

@@ -22,7 +22,7 @@
 
 extern void main(void);
 
-void stage_entry(void) __attribute__((section(".text.stage_entry.armv7")));
+void stage_entry(void) __attribute__((section(".text.stage_entry.arm")));
 void stage_exit(void *);
 void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size);
 

src/arch/arm/romstage.ld

@@ -39,7 +39,7 @@ SECTIONS
 	.romtext . : {
 		_rom = .;
 		_start = .;
-		*(.text.stage_entry.armv7);
+		*(.text.stage_entry.arm);
 		*(.text.startup);
 		*(.text);
 	}

src/console/Kconfig

@@ -2,7 +2,7 @@ menu "Console"
 
 config BOOTBLOCK_CONSOLE
 	bool "Enable early (bootblock) console output."
-	depends on ARCH_ARMV7
+	depends on ARCH_ARM
 	default n
 	help
 	  Use console during the bootblock if supported

src/cpu/Kconfig

@@ -1,7 +1,7 @@
 # Warning: This file is included whether or not the if is here.
 # The if controls how the evaluation occurs.
 # (See also src/Kconfig)
-if ARCH_ARMV7
+if ARCH_ARM
 
 source src/cpu/armltd/Kconfig
 

src/cpu/armltd/cortex-a9/Kconfig

@@ -1,5 +1,5 @@
 config CPU_ARMLTD_CORTEX_A9
-	depends on ARCH_ARMV7
+	depends on ARCH_ARM
 	bool
 	select EARLY_CONSOLE
 	default n

src/device/oprom/yabel/device.h

@@ -128,7 +128,7 @@ u8 biosemu_dev_translate_address(int type, unsigned long * addr);
 static inline void
 out32le(void *addr, u32 val)
 {
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
 	*((u32*) addr) = cpu_to_le32(val);
 #else
 	asm volatile ("stwbrx  %0, 0, %1"::"r" (val), "r"(addr));
@@ -139,7 +139,7 @@ static inline u32
 in32le(void *addr)
 {
 	u32 val;
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
 	val = cpu_to_le32(*((u32 *) addr));
 #else
 	asm volatile ("lwbrx  %0, 0, %1":"=r" (val):"r"(addr));
@@ -150,7 +150,7 @@ in32le(void *addr)
 static inline void
 out16le(void *addr, u16 val)
 {
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
 	*((u16*) addr) = cpu_to_le16(val);
 #else
 	asm volatile ("sthbrx  %0, 0, %1"::"r" (val), "r"(addr));
@@ -161,7 +161,7 @@ static inline u16
 in16le(void *addr)
 {
 	u16 val;
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
 	val = cpu_to_le16(*((u16*) addr));
 #else
 	asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));

src/include/cbfs_core.h

@@ -107,7 +107,7 @@ struct cbfs_header {
  */
 #define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
 #define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARMV7    0x00000010
+#define CBFS_ARCHITECTURE_ARM      0x00000010
 
 /** This is a component header - every entry in the CBFS
     will have this header.

src/lib/rmodule.c

@@ -60,9 +60,9 @@ static inline void *remodule_next_reloc(const void *reloc)
 	return (void *)rel;
 }
 
-#elif CONFIG_ARCH_ARMV7
+#elif CONFIG_ARCH_ARM
 /*
- * On ARMv7, the only relocations currently allowed are R_ARM_RELATIVE which
+ * On ARM, the only relocations currently allowed are R_ARM_RELATIVE which
  * have '0' for the symbol info in the relocation metadata (in r_info).
  * The reason is that the module is fully linked and just has the relocations'
  * locations.

src/mainboard/emulation/qemu-armv7/Kconfig

@@ -23,7 +23,7 @@ if BOARD_EMULATION_QEMU_ARMV7
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select ARCH_ARMV7
+	select ARCH_ARM
 	select CPU_ARMLTD_CORTEX_A9
 	select HAVE_UART_MEMORY_MAPPED
 	select HAVE_UART_SPECIAL

src/mainboard/google/kirby/Kconfig

@@ -21,7 +21,7 @@ if BOARD_GOOGLE_KIRBY
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select ARCH_ARMV7
+	select ARCH_ARM
 	select CPU_SAMSUNG_EXYNOS5420
 	select HAVE_UART_MEMORY_MAPPED
 	select EC_GOOGLE_CHROMEEC

src/mainboard/google/nyan/Kconfig

@@ -21,7 +21,7 @@ if BOARD_GOOGLE_NYAN
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select ARCH_ARMV7
+	select ARCH_ARM
 	select SOC_NVIDIA_TEGRA124
 
 config MAINBOARD_DIR

src/mainboard/google/pit/Kconfig

@@ -21,7 +21,7 @@ if BOARD_GOOGLE_PIT
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select ARCH_ARMV7
+	select ARCH_ARM
 	select CPU_SAMSUNG_EXYNOS5420
 	select HAVE_UART_MEMORY_MAPPED
 	select EC_GOOGLE_CHROMEEC

src/mainboard/google/snow/Kconfig

@@ -21,7 +21,7 @@ if BOARD_GOOGLE_SNOW
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select ARCH_ARMV7
+	select ARCH_ARM
 	select CPU_SAMSUNG_EXYNOS5250
 	select HAVE_UART_MEMORY_MAPPED
 	select EC_GOOGLE_CHROMEEC