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coreboot/src/soc
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Shelley Chen 6b42f2a196 UPSTREAM: soc/intel/skylake: Enable SATA ports 
The current implementation is incorrect and is
actually disabling the ports.  Fixes that.

BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
     SATA SSD.

Change-Id: I908c1ab04b6d5fd823a89bf1a1eae3116920e468
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d44d028050
Original-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19553
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497404
2017-05-07 16:25:49 -07:00
..
broadcom/cygnus UPSTREAM: vboot: Move remaining features out of vendorcode/google/chromeos 2017-03-29 13:43:08 -07:00
dmp/vortex86ex UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
imgtec/pistachio UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING 2017-01-05 11:00:04 -08:00
intel UPSTREAM: soc/intel/skylake: Enable SATA ports 2017-05-07 16:25:49 -07:00
lowrisc/lowrisc UPSTREAM: soc/lowrisc: Place CBMEM at top of autodetected RAM 2016-12-08 12:30:55 -08:00
marvell UPSTREAM: vboot: Move remaining features out of vendorcode/google/chromeos 2017-03-29 13:43:08 -07:00
mediatek/mt8173 UPSTREAM: mediatek/mt8173: Add support for Dual DSI output 2017-04-25 05:52:33 -07:00
nvidia UPSTREAM: lib/edid.c: Differentiate between absent and non-conformant EDID 2017-05-07 07:41:12 -07:00
qualcomm UPSTREAM: Remove libverstage as separate library and source file class 2017-03-29 13:43:09 -07:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip UPSTREAM: lib/edid.c: Differentiate between absent and non-conformant EDID 2017-05-07 07:41:12 -07:00
samsung UPSTREAM: vboot: Select SoC-specific configuration for all Chrome OS boards 2017-03-29 13:43:05 -07:00
ucb/riscv UPSTREAM: soc/ucb/riscv: Place CBMEM at top of autodetected RAM 2016-12-08 12:30:48 -08:00